ReCoSoC 08 - Barcelona, Spain

Start: Jul 9 2008 - 8:00am

End: Jul 11 2008 - 12:00pm

Timezone: Etc/GMT-8

Event/Conference Information URL:

ReCoSoC is a periodic annual meeting to expose and discuss gathered expertise as well as state of the art research around SoC related topics through plenary invited papers and posters. Similarly to past editions, we will have several keynotes given by internationally renowned speakers and special events like tutorials.
Areas of interest:
The Reconfigurable Communication-centric Systems-on-Chip workshop is a forum to present and discuss new research on reconfigurable computing, Systems and Networks on Chips areas.
A wide variety of topics related to Systems-on-Chips are covered, including but not limited to:
- Embedded Reconfigurability in all its forms
- Multi-Processors Systems-on-Chips
- System & SoC design methods
- Communication architectures
- Asynchronous design techniques
- Low-power design methods
- Middleware related approaches
- New paradigms of computation including bio-inspired approaches

Wednesday, July 9th

	8:00 h. - 8:30 h.	Registration
	8:30 h. -8:45 h.	Opening and welcome session
	8:45 h. - 9:45 h.	Keynote 1: Mateo Valero
	9:45 h. - 10:15 h.	Short Break
	10:15 h. - 11:15 h.	Session 1: Design of Reconfigurable Architectures Session Chair: Lionel Torres Design of a BIST-Core Using Cellular Automata for IP-core and Interconnect Testing Rupsa Chakraborty, Dipanwita Roy Chowdhury FPGA Interconnect Topologies Exploration Zied Marrakchi, Hayder Mrabet, Habib Mehrez eFPGA architecture explorations: CAD & Silicon analysis of beyond 90nm technologies to investigate new dimensions of future innovations Syed Zahid Ahmed, Michael Fernandez, Gilles Sassatelli, Lionel Torres
	11:15 h. - 11:45 h.	Coffee Break
	11:45 h. - 13:05 h.	Session 2: Multicore / Multiprocessor System on Chip Session Chair: Gilles Sassatelli Formal Specification and Verification of a Delta-MIN Based Interconnection Architecture for MPSoC Yassine AYDI, Maissa ELLEUCH, Mohamed ABID Reducing Reconfiguration Overheads in Heterogeneous Multi-core RSoCs with Predictive Configuration Management Stéphane Chevobbe, Stéphane Guyetant A Decentralised Task Mapping Approach for Homogeneous Multi-Processor Network-on-Chips Peter Zipf, Gilles Sassatelli, Nurten Utlu, Nicolas Saint-Jean, Pascal Benoit, Manfred Glesner Exploration of Task Migration Policies on the HS-Scale System Gabriel Marchesan Almeida, Nicolas Saint-Jean, Sameer Varyani, Gilles Sassatelli, Pascal Benoit, Lionel Torres
	13:05 h. - 14:30 h.	Lunch
	14:30 h. - 15:30 h.	Poster Session 1 Session Chair: Michael Hübner Accelerating the Search of Good Error Correcting Codes by means of a Parallel Processor Using Reconfigurable Hardware Juan A. Gomez-Pulido, Miguel A. Vega-Rodriguez, Juan M. Sanchez-Perez Performance Estimation Methodology and High Level Design for Heterogeneous Reconfigurable Architectures Rashid Muhammad, le-lann jean-christophe Experimental review of task mapping algorithms for NoC-based Multiprocessor Systems-on-Chip Sameer Varyani, Tianlun Lui, Leandro Indrusiak, Luciano Ost, Leandro Möller, Manfred Glesner Communication Infrastructure for a Self-Adaptive Hardware Architecture Javier Soto, Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany Depth First Traversal Algorithm for Efficient Build-in Self-Test in Nano Fabrics Mahtab Niknahad, Juergen Becker Hardware Accelerated OpenCV on Systems on Chip Felix Mühlbauer, Lucio O. Marchioro Rech, Christophe Bobda A PIPELINED INFRASTRUCTURE FOR THE DISTRIBUTION OF THE CONFIGURATION BITSTREAM IN A COARSE-GRAIN RECONFIGURABLE ARRAY Fabio Garzia, Claudio Brunelli, Jari Nurmi
	15:30 h. - 15:45 h.	Short Break
	15:45 h. - 16:45 h.	Session 3: Streaming Applications and Infrastructure Session Chair: Pascal Benoit A Refinement Case-Study of a Dynamically Reconfigurable Intersection Test Hardware Andreas Raabe, Andreas Nett, Andreas Niers A lightweight SDRAM Controller for Self-Reconfigurable Video Processing Platforms Kurt Franz Ackermann, Burghard Hoffmann, Leandro Soares Indrusiak, Manfred Glesner Adaptive Scheduling of Dynamic Reconfiguration in Stream-Based Applications Ralph Görgen, Frank Oppenheimer, Wolfgang Nebel
	16:45 h. - 17:15 h.	Coffee Break
	17:15 h. - 18:15 h.	Keynote 2: Gregori Vazquez, "Evolution of On-Board Processors (OBP) for Multimedia and TT&C Satellite Payloads"

	Thursday, July 10th

	9:00 h. - 10:00 h.	Keynote 3: Christian Gamrat
	10:00 h. - 10:30 h.	Short Break
	10:30 h. - 11:30 h.	Session 4: Self-Organisation and Bio-inspired Hardware Session Chair: Jordi Madrenas Enabling Self-Organization in Embedded Systems with Reconfigurable Hardware Klaus Drechsler, Jan Schulte, Dominik Murr, Christophe Bobda Emulating Biologically Inspired Architectures in Hardware: A New Reconfigurable Paradigm for Computation Jim Harkin, Fearghal Morgan, Steve Hall, Liam McDaid On-Line Communication Mechanisms for Self-adaptive and Self-reconfigurable Systems J. Manuel Moreno Arostegui, Jordi Madrenas, Joan Cabestany, Katarina Paulsson, Michael Huebner, Juergen Becker
	11:30 h. - 12:00 h.	Coffee Break
	12:00 h. - 13:00 h.	Session 5: Self-Reconfiguration and Simulation Session Chair: Loic Lagadec An Interface for a Decentralized 2D-Reconfiguration on Xilinx Virtex-FPGAs for Organic Computing Christian Schuck, Bastian Haetzer, Jürgen Becker Multi-Level Simulation of Heterogeneous Reconfigurable Platforms Damien Picard, Loic Lagadec Self-Reconfiguration of Embedded Systems Mapped on Spartan-3 Enrique Canto, Mariano Lopez, Francesc Fons
	13:00 h. - 14:30 h.	Lunch
	14:30 h. - 15:30 h.	Session 6: Mapping and Programming Models Session Chair: Peter Zipf High Level Modeling of Partially Dynamically Reconfigurable FPGAs based on MDE and MARTE Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser Design Flow for Reconfigurable MicroBlaze Accelerators Jiri Kadlec Process System Modeling for RSoC Damien Picard, Bernard Pottier, Ciprian Teodorov
	15:30 h. - 16:00 h.	Coffee Break
	16:00 h. - 17:00 h.	Poster Session 2 Session Chair: Michael Hübner Task-graph management for reconfigurable multi-tasking systems Juan Antonio Clemente, Carlos González, Javier Resano, Daniel Mozos JopCMP - A Java Chip-Multiprocessor for Real-time Systems Christof Pitter Preemptive HW/SW-Threading by combining ESL methodology and coarse grained reconfiguration Marko Roessler, Ulrich Heinkel High Performance Reconfigurable Blocks for Real-Time Reconfigurable Unit (ADAPTO) Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re FPGA Based Stepper Motor Control Function Exploiting Run-Time Reconfiguration Nadine Dahm, Michael Huebner, Juergen Becker DRNoC, an On-chip Communication Solution for partial Runtime Reconfigurable Systems Yana Krasteva, Eduardo de la Torre, Teresa Riesgo
	17:00 h. - 18:30 h.	Panel session: "MPSoCs going from multi to many: how and why?"
	21:00 h.	Social Event

	Friday, July 11th

	9:00 h. - 10:00 h.	Keynote 4: Panagiotis Tsarchopoulos, "An Overview of the European ICT Research Programme and Prospects for Reconfigurable Computing"
	10:00 h. - 10:30 h.	Coffee Break
	10:30 h. - 11:30 h.	Session 7: Wireless Communication Applications Session Chair: J. Manuel Moreno WIMAX LDPC Codec on Coarse Grained Reconfigurable XPP Architecture Mahendra kumar Angamuthu Ganesan, Andrej Rikovsky, Frank May, Jürgen Becker A SOPC Architecture for Data-dependent Superimposed Training Channel Estimation Fernando Martin del Campo, Rene Cumplido, Roberto Perez-Andrade, Aldo Orozco-Lugo
	11:30 h. - 12:00 h.	Closing session