The Verilog hardware description language plays a key role in design
flows for ASICs and FPGAs. It is increasingly important that people
involved with hardware design have a background in this language and an
awareness of the features introduced by IEEE Std 1364-201. This course
provides a basic introduction to the main features of the Verilog
language. The course will familiarize the student with the language and
bridge the gap between the basic concepts in digital logic (schematics,
Boolean equations, truth tables, etc.) and related constructs used in
Verilog-based design flows. Several examples will illustrate language
features, including an introduction to modeling styles suitable for
synthesis and verification.