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FPGA Workshop 2008 - Yverdon, Switzerland
This workshop will teach you best practices and new techniques that
will make it possible for you to design, verify and integrate FPGAs to
meet all of your design and project goals while using Mentor Graphics'
best in class FPGA design and verification tools : HDL Designer,
Modelsim/Questa, Precision Synthesis Plus and I/O Designer.
Mentor's application specialists will assist you to work through seven labs with PCs and software being provided:
Lab 1) Introduction of complete design flow
Lab 2) RTL design check and verification with "self-checking testbench" using enhanced verification techniques
Lab 3) RTL Synthesis with SDC constraints
Lab 4) Timing Analysis and incremental Timing Analysis after P&R (new physical aware synthesis enabled by Precision RTL Plus)
Lab 5) Interface Data exchange with PCB environment featuring I/O Designer
Lab 6) Physical Synthesis ECO
Lab 7) Design Implementation with different FPGA technologies (Retargeting)
FPGA Webcasts
Upcoming FPGA Events
- The Fourth Annual Reconfigurable Systems Summer Institute (RSSI'08) - Urbana, IL(Event or Conference)(2 days)
- AVMS VI-01: An Introduction to Transaction Level Modeling in SystemC(Event or Conference)(5 days)
- ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS - ERSA’08 - Las Vegas, Nevada(Event or Conference)(9 days)
- AVMS VI-02: Practical Examples of PSL Usage(Event or Conference)(12 days)
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