World's 1st FPGA/CPLD Portal

Session 1
Does the inexperienced beginners' class person how
design FPGA of functional full load?

If the beginner, when beginning the FPGA design,
how uses with what kind of function in FPGA, it is good? You
explain from the foundation of the device, when really designing,
concerning the point where the beginner is easy to fall.

Session 2
Application of physical synthesis for design efficiency
and quality improvement

With the FPGA development where large-scale
acceleration advances, timing focus is difficult, long-term conversion
of design period has become problem. It introduces this time,
concerning the application case of the physical synthesis which as
solution of the above-mentioned problem it tackles.

Session 3
The specification modification which occurs frequently
correspondence to the low power request which impends

The FPGA device and that development tool have
raised everyday functional efficiency. The design engineer not
only managing those, must learn the design technique which is adapted
to high accumulation & high function. Correspondence to the
specification change request which especially occurs shortly in
payment date and, low correspondence to electric power consumption
conversion has become recent topic. As a help of the solution,
the designer on of site same incremental design low it can apply game
electric power consumption design Clock Domain while mixing the
different and applied case due to FPGA and ASIC explains up-to-date
design technique such as Crossing risk management design.

Session 4
The baseplate design (structure) with the know-how which
moves FPGA!

In order for FPGA to move from the gaze of the
commodity developer, ' the baseplate design is designated as this way,
that ' it introduces with stance.

Session 5
Actual efficiency and the application method of the
processor which is loaded onto FPGA

Due to the evolution of FPGA environment of here
several years, it reached the point where the installed system which
loads the processor onto FPGA can be constructed easily. It is
possible to actualize multiprocessor and various bus structures by the
fact that it utilizes degree of freedom of FPGA, but you verify
whether some kind of system configuration can show the performance of
FPGA efficiently.

Session 6
The design verification which uses the up-to-date FPGA
prototype board

The up-to-date large-scale FPGA device LVDS
transfer high-speed serial has loaded I/O and the like of high speed
many functions. In addition there is also a prototype board
which exceeds the 20M gate in the one for verification of large-scale
ASIC. How using these prototype boards effectively, whether it
does design verification, you explain.

Session 7
Effectiveness of the FPGA design due to C language and
how to advance the hard software cooperation design

In at this lecture, C language program of the
micro-computer is explained to example concretely concerning the
effectiveness of the FPGA design which first uses C language. It
utilizes the merit which can be dropped into the hardware of FPGA from
C language and in the future, vis-a-vis the system and the software
which are enlarged, how keeps executing the cooperation design of the
hard software well, concerning whether it should, you explain.

Session 8
Present condition and development example of the system
which utilizes the part reconstruction of FPGA

Here several years, research and development of
the system which utilizes "the part reconstruction" of FPGA has spread
quickly. While maintaining the high processing efficiency where
by the fact that part reconstruction is utilized, it is by the private
hardware, adjusting to use and environment, it is expected that it can
actualize the reduction of the soft system and the circuit area
electric power consumption where the circuit changes and the
correction etc. after the trouble vulnerability shipping. In at
this lecture, it explains concerning the part reconstruction
functional feature and advantage of FPGA, introduces the applied
example of the resistance breakdown system and the like. In
addition, the contents transmission system which utilizes part
reconstruction as a detailed development example, is introduced.

Chairmanship: Hasegawa Takashi JEITA SystemC
working group investigation committee chairman [ Fujitsu ]

As for SystemC, the standard IEEE of SystemC after
1666-2005 is approved, the release and the like of OSCI SystemC2.2 and
TLM2.0 is done in 2005 December in IEEE, furthermore the range of
activity is spreading. And presently and as a de facto standard
of C language based system level design language, it is widely
utilized in verification and design field, in the future further
expectation is moved aside. With this session, 1) SystemC update
and the TLM2.0 tutorial by OSCI, 2) report of the match regarding
SystemC based TLM2.0 by the JEITA SystemC working group, 3) it
announces the design case which uses SystemC.

• OSCI update: Patric Sheridan (OSCI)
• TLM2.0 tutorial: Thorsten Grötker (OSCI)
• The match regarding TLM2.0: SystemC working
  group
• Utilizes TLM software early development:
  Kazumasa Nakamura [ Fujitsu ]

- Up-to-date system LSI it is low electric power
consumption design technology - the place where you expect to
standardization -
Nobuyuki Nisiguti [ development 1st Department Manager
STARC execution official ]

Up-to-date system LSI low in the electric power
consumption design, it has become necessary to use multiple power
source, combining, various technologies such as use, clock gating,
power gating, vector less electrical calculation and the transistor
gate major key paragraph of multiple threshold voltage. In at
this lecture, this low we explain the present condition of the
technology which makes the electric power consumption design possible.
In addition, it controls efficiently not to make a mistake in
the combination of these technologies, it is necessary to use the
system of being standardized concerning the importance and the place
where you expect it expresses.

- Unified POWER Format (UPF) the forum (simultaneous
interpretation you attach)

Today, electric power consumption has become one
of most important topics for the architecture charge and design charge
of system LSI. So far, each EDA vendor each user corresponding
to the needs to the electric power consumption design low, defined the
format of individual specification, in addition the user had designed
making use of those. But, this plural formats had caused mistake
and a following leak etc. to specification modification which come
from the fact that loss and description of coherence of design flow
become redundant.
Vis-a-vis the definition demand of the standard POWER Format to
which UPF with DAC 2006 was put out from many users, covers low the
electric power consumption design to GDSII from RTL, Accellera
(?????) it is something which is decided in 2007 February.
Presently the group of vendors, that in flow of the electric
power consumption design, support UPF low.
With this forum, total to mounting low it introduces the
electric power consumption design solution and the case from the
architecture specification which designates UPF as pivot.

• Chairmanship /Introduction:
  Dennis Brophy [ Accellera and Vice-Chair ]
• Architecting a low POWER design with UPF:
  Matt Fisch [ Synopsys and Senior Director of Low POWER Solutions
  Marketing ]
• Functional verification of a low POWER design:
  Synthesizing and implementing the low POWER design:
  Arvind Narayanan [ Magma Design Automation and Product Director
  ]
• Case: UPF Experience & Conclusion:
  Yatin Trivedi [ Magma Design Automation ]

- Common POWER Format (CPF) forum

The Cadence corporation lectures CPF and, is
decided by the standardization group POWER Forward Initiative which is
established, presently it is the Low POWER design format which is
recognized as the standard of Si2. With this forum, the
background of CPF standardization and as you express the activity
circumstance by the recent Si2 Low POWER Coalition group concerning,
we introduce the application example of CPF. The total which
power source cutoff and the multi power source designs etc. confronts
the leading Low POWER design which is complicated, designates CPF to
logical verification test design synthesis arrangement wiring sign off
analysis as pivot by the fact that the concrete application case of
CPF by design solution, and STARC and the NEC micro system is
introduced, in design flow it shares and we explain the advantage of
the thing which utilizes standard format CPF.

• Chairmanship /Introduction: Jake Buurma [ Si2, VP ]
• The summary of CPF and the Low POWER design
  environmental solution which utilizes CPF:
  Suzuki [ the Japanese Cadence design systems
  corporation senior technical marketing manager ]
• Case 1: STARCAD-CEL RPIDE V1.5 low power
  design flow:
  Yoshiaki Sugioka [ STARC development 1st section team leader ]
• Case 2: Ultimate after the 65nm/55nm
  generation aiming toward electric power consumption SoC design
  technology low,:
  Kikuchi [ NEC micro system basis core development
  division chief ]

- The match of JEITA to of POWER Format

Yamada paragraph person JEITA EDA standardization
sub-committee investigation committee chairman [ Sanyo Electric ]