Sixteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays - Monterey, CA

Start: Feb 24 2008 - 2:00pm

End: Feb 26 2008 - 6:00pm

Timezone: Etc/GMT-8

Event/Conference Location:

Monterey Beach Resort, Monterey, CA

Event/Conference Information URL:

The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays is the premier conference for presentation of advances in all areas related to FPGA technology.

Preliminary Program

	Sunday, February 24, 2008
	Pre-conference Workshop
2:00 PM	To be announced


	Reception
6:00 PM	Registration
7:00 PM	Welcome Reception

	Monday, February 25, 2008

8:00 AM	Continental Breakfast
	Registration

8:40 AM	Opening Remarks

9:00 AM	Session 1: Physical Design
	Architecture-Specific Packing for Virtex-5 FPGAs Taneem Ahmed, Paul Kundarewich, Jason Anderson, Brad Taylor and Rajat Aggarwal Xilinx, Inc.
	High-Quality, Deterministic Parallel Placement for FPGAs on Commodity Hardware Adrian Ludwin, Vaughn Betz and Ketan Padalia Altera Corp.
	Enforcing Long-Path Timing Closure for FPGA Routing with Path Searches on Clamped Lexicographic Spirals Keith So University of New South Wales

10:00 AM	Poster Session 1

11:00 AM	Session 2: Technology Mapping
	Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs Michael Frederick and Arun Somani Iowa State University
	WireMap: FPGA Technology Mapping for Improved Routability Stephen Jang, Billy Chan, Kevin Chung and Alan Mishchenko Xilinx, Inc. and University of California, Berkeley
	Mapping for Better Than Worst-Case Delays In LUT-Based FPGA Designs Kirill Minkovich and Jason Cong University of California, Los Angeles

Noon	Lunch

2:00 PM	Session 3: Simulation Acceleration
	Lithographic Aerial Image Simulation with FPGA-Based Hardware Acceleration Jason Cong and Yi Zou University of California, Los Angeles
	Accelerating Architectural-level, Full-System Multiprocessor Simulations using FPGAs Eric Chung, Eriko Nurvitadhi, James Hoe, Ken Mai and Babak Falsafi Carnegie Mellon University
	A-Ports: An Efficient Abstraction for Cycle-Accurate Performance Models on FPGAs Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Joel Emer and Arvind MIT

3:00 PM	Poster Session 2

4:00 PM	Session 4: Synthesis at Higher Level Abstractions
	Efficient ASIP Design for Configurable Processors with Fine-Grained Resource Sharing Quang Dinh, Deming Chen and Martin Wong University of Illinois at Urbana-Champaign
	Pattern-Based Behavior Synthesis for FPGA Resource Reduction Jason Cong and Wei Jiang University of California, Los Angeles
	C is for Circuits: Capturing FPGA Circuits as Sequential Code for Portability Scott Sirowy, Greg Stitt and Frank Vahid University of California, Riverside

7:00 PM	Dinner and Evening Panel
	To be announced

8:00 AM	Continental Breakfast
	Registration

	Tuesday, February 26, 2008

8:50 AM	Session 5: Architecture Tools
	TORCH: A Design Tool for Routing Channel Segmentation in FPGAs Mingjie Lin and Abbas El Gamal Stanford University
	Modeling FPGA Routing Demand in Early-Stage Architecture Development Wei Mark Fang and Jonathan Rose University of Toronto
	Area and Delay Trade-offs in the Circuit and Architecture Design of FPGAs Ian Kuon and Jonathan Rose University of Toronto
	Trace-Based Framework for Concurrent Development of Process and FPGA Architecture Considering Process Variation and Reliability Lerong Cheng, Yan Lin, Lei He and Yu Cao University of California, Los Angeles and Arizona State University

10:10 AM	Poster Session 3

11:10 AM	Session 6: Architecture
	A Novel FPGA Logic Block for Improved Arithmetic Performance Hadi Parandeh-Afshar, Philip Brisk and Paolo Ienne Swiss Federal Institute of Technology (EPFL)
	Architectural Improvements for Field Programmable Counter Arrays: Enabling Efficient Synthesis of Fast Compressor Trees on FPGAs Alessandro Cevrero, Pangiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Verma, Philip Brisk, Frank Gurkaynak, Yusuf Leblebici and Paolo Ienne Ecole Polytechnique Federale de Lausanne (EPFL)
	The Amorphous FPGA Architecture Mingjie Lin Stanford University

12:10 PM	Lunch

1:40 PM	Session 7: Reconfigurable Computing
	Reconfigurable Computing for Learning Bayesian Networks Narges Bani Asadi, Teresa H. Meng and Wing H. Wong Stanford University
	HybridOS: Runtime Support for Reconfigurable Accelerators John Kelm and Steve Lumetta University of Illinois at Urbana-Champaign
	Vector Processing as a Soft-core CPU Accelerator Jason Yu, Guy Lemieux and Christopher Eagleston University of British Columbia

2:40 PM	Break

3:10 PM	Session 8: Random Number Generators
	FPGA-optimised high-quality uniform random number generators David Barrie Thomas and Wayne Luk Imperial College
	A Hardware Framework for Fast Generation of Multiple Long-period Random Number Streams Ishaan Dalal and Deian Stefan The Cooper Union

3:50 PM	Closing Remarks