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DVCon is the premier conference for functional design and verification
of digital electronic systems. The conference has grown from its days
as user groups focused on HDLs to a full-fledged conference featuring
the latest technology, techniques, standards and methods. Through our
desire to enhance the value of the conference and to ensure a high
quality program, we have provided innovations including sponsored
tutorials, embedded tutorials, academia research sessions and
refinements in the overall conference experience through locating
parallel tracks in rooms in physical proximity and sponsored luncheons
and events featuring educational and entertaining programs.

The 2008 DVCon Conference promises to be the best attended one in many
years. Issues related to design and verification continue to be at the
forefront of the problems that need to be solved in the EDA market. We
must, as an industry, deliver breakthrough solutions that will allow
EDA customers to produce new designs in a manner that optimizes their
profit margins, if we are to be perceived as strategic partners in
their business model. Innovation may not be enough; we need invention
to put us on pace with the continuing progress in silicon fabrication
technology.

The design and verification solutions must address different levels
of abstraction concurrently, must deal successfully with
hardware/software co-development, and must be multi-lingual because the
application areas require the use of different languages like Java, C,
Verilog, VHDL, SystemC, and SystemVerilog.

Wednesday Sessions:

February 20, 2008

8:00am-7:00pm Registration (Bayshore Foyer)

8:30	Opening Session (Oak Ballroom)
8:45
9:00	Session 1 (Fir Ballroom) Verification of Low-Power Designs	Session 2 (Oak Ballroom) Applications of the System Verilog Direct Programming Interface
10:30
	Break
11:00	Session 3 (Fir Ballroom) Assertion-Based Verification of Low-Power Designs	Session 4 (Oak Ballroom) SystemC in Verification
12:30
12:30	Lunch and Presentation (Pine/Cedar Ballroom) sponsored by:
1:30
2:00	Keynote (Oak/Fir Ballroom) Ending Endless Verification Walden C. Rhines - Chief Executive Officer and Chairman of the Board of Directors, Mentor Graphics Corp.
2:45
	Break
3:00	Panel Session (Oak/Fir Ballroom) Troublemaker's Panel
4:30
4:30	Reception (Bayshore Ballroom) sponsored by:

Thursday Sessions:

February 21, 2008

7:00am-4:00pm Registration (Bayshore Foyer)