World's 1st FPGA/CPLD Portal

Presenter: Ashok Mehta, DefineView Consulting
Ashok Mehta has worked in the semiconductor industry for the past 24+ years in hardware design and verification engineering / management positions at companies such as Digital, Data General, Intel, IKOS, Philips Semiconductor, AMCC and many startups. Ashok has been a member of technical sub-committees on IEEE Verilog, SDF, and EIA 576. He brings real life experience as a user of HDL and HVL languages and methodologies to the training class.

Abstract:
System Verilog Assertions (SVA) is a powerful subset of the IEEE 1800 System Verilog standard. Its hardware oriented concurrent semantics allow for intuitive development of complex multi-clock domain checkers to catch those elusive bugs at the source. It allows for clean separation from the design logic and allows for parameterization of properties resulting in a modular reusable methodology.

Functional Coverage (FC) is another subset of System Verilog that allows you to measure how much of design intent have you covered with your tests/regressions. Combined SVA and FC allow for a modular, reusable and objective methodology that shortens time to develop&debug and gain much higher confidence in delivering a first pass working silicon.

Agenda:
SVA Methodology
o What's an assertion?
o What are the advantages of SVA?
o Assertion Based Verification (ABV) Methodology Guidelines

SVA Language Overview
o Immediate assertions
o Concurrent assertions
o Basics (implication operator, formal args, severity levels, disable iff, etc.)
o Binding design module to property module
o Sampled value functions ($rose, $fell, $stable, $past)
o Operators (clock delay, consecutive, repetition, non-consecutive, goto)
o Sequence 'within', 'throughout', 'and', 'intersect', 'or', 'not', 'firstmatch'
o If… else
o System Functions ($onehot, $isunknown, etc.)/System Tasks ($asserton, $assertoff, etc.)
o .ended, .matched methods to detect endpoint of a sequence
o Multi-Clocked properties
o Local Variables
o Recursive properties
o embedding concurrent assertions in procedural code; calling subroutines; etc.

Functional Coverage Overview
o Code Coverage vs. Functional Coverage
o Brief overview of covergroup, coverpoint, cross, transition with simple applications

Time: 1:00 pm to 5:00 pm

Cost: $199

Refreshments:
Afternoon Break with coffee, tea, decaf, soft drinks, bottled water, fresh whole fruit and a selection of sweet and savory treats.

Location:
Santa Clara Network Meeting Center
5201 Great America Parkway
Santa Clara CA. 95054