World's 1st FPGA/CPLD Portal

Engineers reuse existing RTL to hit tighter schedules and reduce costs. Over 80% of ASIC and FPGA designs reuse RTL from a previous design. However, existing RTL is rarely well documented, and can be so difficult to understand that engineers will rewrite it rather than reuse it -- losing expensive design work. HDL Designer allows engineers to quickly understand and evaluate existing RTL. HDL Designer provides a snapshot of the RTL's hierarchy, functionality, and quality; reducing the RTL learning curve and helping to successfully reuse existing RTL.

An effective RTL Reuse process involves:

* Using scoring to gauge how easy/hard/long it will be to use unfamiliar RTL
* Finding missing files, dependencies, etc. to make sure you have all the pieces
* Employing visualization to understand and document a design
* Making it quick and easy to use: One click loading, and other scripted operations

To learn how you can save time and improve the quality of your design through RTL Reuse, Mentor Graphics cordially invites you to attend a FREE "Lunch & Learn" seminar.
Who Should Attend

* Design engineers doing digital IC design
* Engineering and project managers

What You Will Learn

This session will take you through a typical RTL Reuse process and highlight areas where trade-offs are often made, providing an overview on:

* Determining design integrity
* Assessing the design’s quality
* Creating various visualizations of the design
* Making necessary changes to the design