World's 1st FPGA/CPLD Portal

An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Prototcol (IP) routers using hardware rather than software. The platform can be used by researchers to prototype advanced services for next-generation networks.

By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During summer camp, we will use the NetFPGA to determine the amount of memory needed to buffer TCP/IP data streaming through the Gigabit/second router. Hardware circuits within the NetFPGA will be implemented to measure and plot the occupancy of buffers. Circuits will be downloaded into reconfigurable hardware and tested with live, streaming Internet video traffic.

Background
Attendees will utilize a Linux-based PC equipped with NetFPGA hardware. A basic understanding of Ethernet switching and network routing is expected. Past experience with Verilog is useful but not required. This week-long summercamp extends the material presented at the NetFPGA tutorials. Participants will be able to take home their NetFPGA systems at the end of the week-long camp.

Outline

* Day 1 (Monday, Aug. 4)
o Welcome to the lab, introductions to staff, faculty, students
o Overview of routers and the NetFPGA
o Router data and control planes
o Routing Protocols
o Introduction to OpenFlow
o Router architecture
o Address Lookup
o PW-OSPF
o Network of routers
o Java-based Graphical User Interface (GUI)
o Demonstration of High Definition (HD) video streaming

* Day 2 (Tuesday, Aug. 5)
o Field Programmable Gate Array (FPGA) Logic
o Random Access Memory (RAM)
o Verilog Hardware Description Langauge (HDL)
+ Registers, integers, arrays
+ Multiplexers
+ Synchronous storage elements
+ Finite State Machines (FSMs)
o Hardware Debug
o Working with OpenFlow modules
o Buffer Size Experiment
o Adding the event capture module
o Configurating of the Rate limiter module

* Day 3 (Wednesday, Aug. 6)
o Assign team groups
o Work on Projects
o NetFPGA group members available to answer questions

* Day 4 (Thursday, Aug. 7)
o Work on Projects
o NetFPGA group members available to answer questions

* Day 5 (Friday, Aug. 8)
o Present Projects to the group
o Award prizes for the best projects