On-chip user memory has become a common resource on modern FPGAs. This memory comes in the form of configurable Embedded Memory Blocks (EMB). EMBs are very area efficient for implementing designs
a day of Verification. Sessions covering
everything from CDC, Verification Management, Processor Based
Verification, Low Power, Testbench Automation, Formal Techniques and
the Open Verification Methodology. Don't miss the chance find out how
Mentor Graphics is changing the direction of Verification to keep you
ahead of the game.
Time
Topic and Sessions
8:30 - 9:00
Check-in & Registration
9:00
- 10:15
Introduction:
Make Functional Verification your Competitive Differentiator
10:15 - 10:30
Break | Attendees to Decide Next Session Participation
10:30 -11:15
CDC Verification
-or-
Verification Management
11:15 - 11:25
Break | Attendees to Decide Next Session Participation
11:25 - 12:15
Open Verification Methodology
-or-
Processor Based Verification
12:15 - 1:00
Lunch | Attendees to Decide Next Session Participation
1:00 - 1:45
TLM for SoC Design and Verification
-or-
Low Power Verification
1:45 - 1:55
Break | Attendees to Decide Next Session Participation