World's 1st FPGA/CPLD Portal

Presenter - Ashok Mehta, DefineView Consulting
Ashok Mehta has worked in the semiconductor industry for the past 24+ years in hardware design and verification engineering / management positions at companies such as Digital, Data General, Intel, IKOS, Philips Semiconductor, AMCC and many startups. Ashok has been a member of technical sub-committees on IEEE Verilog, SDF, and EIA 576. He brings real life experience as a user of HDL and HVL languages and methodologies to the training class.

Abstract
System Verilog Assertions (SVA) is a powerful subset of the IEEE 1800 System Verilog standard. Its hardware oriented concurrent semantics allow for intuitive development of complex multi-clock domain checkers for your design and significantly reduces time to debug because assertions directly point to the source of the bug. SVA allows for a modular and reusable methodology that shortens time to develop & debug and gain much higher confidence in delivering a first pass working silicon.
Agenda
Methodology
· What's an assertion? SVA advantages.
· Assertion Based Verification Methodology
Language Overview
· Immediate assertions
· Concurrent assertions (with examples and applications)
· Basics (implication operator, formal args, severity levels, disable iff, etc.)
· Binding design module to property module
· Sampled value functions ($rose, $fell, $stable, $past)
· Operators (clock delay, consecutive, repetition, non-consecutive, goto)
· Sequence 'within', 'throughout', 'and', 'intersect', 'or', 'not', 'firstmatch'
· If… else
· System Functions ($onehot, $isuknown, etc.)
· System Tasks ($asserton, $assertoff, etc.)
· Multi-Clocked properties
· Local Variables