EDA Tech Forum - Seoul, Korea

Start: Aug 29 2008 - 9:00am

Timezone: Etc/GMT-8

Where:

Seoul, Korea

Event/Conference Information URL:

Traveling to over 15 cities worldwide, the EDA Tech Forum series is the largest EDA industry event, bringing together over 7,500 attendees every year from over 2,250 companies. It provides an excellent opportunity for EE designers and engineers to network with their peers and, conversely, for EDA solution providers to reach those markets. The FREE, one-day format includes:

    * Industry expert keynotes discussing the latest EDA issues
    * Hands-on workshops where attendees can test drive new tools
    * A Vendor Fair with solution providers demonstrating new products
    * Technical sessions focusing on the design areas of:
    *
          o Low Power: ESL to RTL
          o Low Power: RTL to FAB
          o High Performance Systems Design
          o Achieving Yeild for High Performance and Low Power

Time	Track 1 Low Power -ESL to RTL -	Track 2 Low Power -RTL to FAB -	Track 3 High Performance Systems Design	Track 4 Achieving Yield for High Performance and Low Power
09:00-09:50	Registration / Vendor Fair
09:50-10:00	Welcome Speech
10:00-10:40	Keynote Speech - A Demographic Driven Design Evolution - Wally Rhines / CEO & Chairman, Mentor Graphics
10:40-11:20	Special Guest Speech - ??? ?? - ??? / ???
11:20-11:30	Breakout
11:30-12:20	Scalable TLM Platform Solution for Low Power Design - Alon Wintergreen	Kick Starting Power Aware Verification at the RTL - Alan Ma	High Performance Design Using FPGAs - Xilinx / Steve Park	Evolving Physical Verification to Maximize Yield - Myron Lin
12:20-13:30	Lunch / Vendor Fair
13:30-14:20	High-Level Synthesis: Synthesizing Multiple Clock Domains to Achieve Low Power - Tom Nagler	Delivering High Performance and Low Power using Multiprocessing in Embedded Applications - ARM	Advanced Fabrication for Performance - Joe Krolla	2D and 3D Variability Optimization - Myron Lin
14:20-14:40	Break / Vendor Fair
14:40-15:30	Rapid FPGA Design and Implementation Using Model-Based Design - The MathWorks / Yong Jeong Kim	Verification Strategies for Mixed-Signal SoCs - J. J. Maa	Seamless DDR2 Design - Ryan Chang	Critical Test Challenges at 45nm and Beyond - T.P.Tai
15:30-16:20	How to Find the Bugs Missed by Simulation - Rindert Schutten	Multi-Corner-Multi-Mode P&R for Timing, Power, and SI Closure - Lea Koo	Expedition with real customer cases - Glenn Son	Common Platform’s Yield Enhancement Methodology for Advanced Technology Nodes-an IBM, Chartered and Samsung Approach - Common Platform
16:20-16:40	Lucky Draw / Closing