EDA Tech Forum - Hsin-Chu, Taiwan

Power Implications of Implementing Logic Using FPGA Embedded Memory Blocks

September 10, 2008 - 4:03pm — scottc

On-chip user memory has become a common resource on modern FPGAs. This memory comes in the form of configurable Embedded Memory Blocks (EMB). EMBs are very area efficient for implementing designs

What OnChip Embedded Logic Analyzer do you use?

January 28, 2008 - 4:54pm — fc

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Start: Aug 27 2008 - 9:00am

End: Aug 27 2008 - 5:00pm

Timezone: Etc/GMT-8

Where:

Hsinchu Ambassador Hotels, Hsin-Chu, Taiwan

Event/Conference Information URL:

Click here to Register

Traveling to over 15 cities worldwide, the EDA Tech
Forum series is the largest EDA industry event, bringing together over
7,500 attendees every year from over 2,250 companies. It provides an
excellent opportunity for EE designers and engineers to network with
their peers and, conversely, for EDA solution providers to reach those
markets. The FREE, one-day format includes:

Industry expert keynotes discussing the latest EDA issues
Hands-on workshops where attendees can test drive new tools
A Vendor Fair with solution providers demonstrating new products
Technical sessions focusing on the design areas of:
- Low Power: ESL to RTL
- Low Power: RTL to FAB
- High Performance Systems Design
- Achieving Yeild for High Performance and Low Power