World's 1st FPGA/CPLD Portal

An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Prototcol (IP) routers using hardware rather than software. The platform can be used by researchers to prototype advanced services for next-generation networks.

By using Field Programmable Gate Arrays (FPGAs), the NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. During the tutorial, we will use the NetFPGA to determine the amount of memory needed to buffer TCP/IP data streaming through the Gigabit/second router. Hardware circuits within the NetFPGA will be implemented to measure and plot the occupancy of buffers. Circuits will be downloaded into reconfigurable hardware and tested with live, streaming Internet video traffic.

This full-day hands-on tutorial will be held in a classroom or laboratory equipped with ten PCs with NetFPGA hardware on Sunday or Monday, August 17 or 18, 2008.
Background
Attendees will utilize a Linux-based PC equipped with NetFPGA hardware. A basic understanding of Ethernet switching and network routing is expected. Past experience with Verilog is useful but not required. This full-day tutorial extends the material presented at the Hot Interconnects tutorial and the SIGMETRICS tutorials in 2007.

Outline

* Introduction to the operation of an Internet Router
o Control plane
+ Routing protocols
+ Routing table
+ Management interfaces
o Datapath
+ Longest Prefix Match (LPM)
+ Classless Interdomain Routing (CIDR)
+ Header processing
+ Packet buffering

* The NetFPGA Router
o Hardware
+ Gigabit Ethernet interfaces
+ Field Programmable Gate Array (FPGA) Logic
+ Random Access Memory (RAM)
o Software
+ Kernel-space driver
+ User-space applications
+ PCI host interface
o System configuration

* Demonstration Topology
o Hardware
+ Network of ten routers
+ Ethernet switch
+ Video server
+ High Definition (HD) video client
o Software
+ PW-OSPF
+ Routing tables
+ Dynamic re-routing

* Integrated Circuit Design
o Technologies
+ Look-Up Tables (LUTs)
+ Configurable Logic Blocks (CLBs)
+ Field Programmable Gate Arrays (FPGAs)
o Verilog Hardware Description Langauge (HDL)
+ Registers, integers, arrays
+ Multiplexers
+ Synchronous storage elements
+ Finite State Machines (FSMs)
o Hardware Debug
+ Waveform monitor
+ In-circuit logic emulation

* NetFPGA System Components
o Synthesis of tutorial router
o Java-based Graphical User Interface (GUI)
+ Configuration
+ Statistics
o Router architecture
+ Pipeline
+ Queues

* Buffer Size Experiment
o Experiment with TCP/IP flows
+ Rule-of-thumb for the buffer size
+ Round-trip propation delay
+ Capacity of bottlneck link
+ Number of active flows
o Lower delay with smaller queues

* Enhanced Router
o Additional hardware
+ Event capture module
+ Rate limiter
+ Delay module
o Experiments
+ Netperf
+ HD video transport
o Life of packet through the system
+ Description of blocks
+ Waveforms from logic analyzer