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Unique Solutions for a Demanding Market Space
July 22, 2008 - 12:18pm — ikhozamConsumer Handheld Challenges
Traditionally, FPGAs have avoided the consumer handheld market during to its stringent requirements for low power, low cost, and small space. As consumer electronics become more sophisticated, new technology breakthroughs in manufacturing, packaging, and display solutions emerge. Market dynamics remain affected by the same factors: price, power and space.
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Aldec AVMS VI-05: Best Practices for Quick Closure of Verilog Designs
Presenter: Aldec
Abstract: When you design ASIC you have to deal with the tangled reset circuits, multiple clock domain circuits, power dissipation, and other complex issues. In this presentation we will discuss the best design practices for the proper reset circuit, avoiding glitches in cross domain data paths, special consideration for using gated clocks in your design, and some coding techniques for the most efficient verification of the design. Following these practices insures the absence of hard to find bugs later in the design process and eventually help avoiding costly ASIC re-spins.
Agenda:
• Designing the reset circuit that can propagate to all flip flops of the system
• Avoiding meta-stability in multiple clock domain data paths
• Special considerations for using gated clocks
• DFT considerations
• Verification techniques
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