World's 1st FPGA/CPLD Portal

Motivated by the success of recent years, we invite you this year to the sixth ModelSim Verification User Group in Germany. The technical event gives the practical benefits of the various current verification methods and enables the verification efficiency for FPGA and ASIC designs to be targeted. The User Group is in technical lectures, workshops and round table below.

Themes

* Trends of future products - requirements of digital convergence of design and verification.
* Verification flow based on ModelSim and Questa, Technical Update.
* Open Verification Methodology - introduction to the concept of open source, standards-based verification methodology.
* Workshops: Current verification methods:
o Assertion-based Verification with PSL and SystemVerilog
o Constraint Random Verification with SystemVerilog or SystemC
o Functional Verification and Coverage
o Unified Coverage Database UCDB - Verification Management
o Power Aware simulation - Unified Power Format (UPF).
* Workshop: testbench generation with object-oriented programming (OOP) in SystemVerilog and SystemC.
* Clock Domain Crossing verification of complex designs
* Workshop: FPGA with embedded soft processor core: ARM Cortex-M1 as ModelSim / link code verification flow.
* System modeling and simulation in distributed mechatronic systems.

Agenda

08:30 - 09:00 Registration
09:00 - 09:15 Welcome by TRIAS and Mentor Graphics
09:15 - 09:45 Trends of future products - requirements of digital convergence of design and verification.
09:45 - 10:15 Verification flow based on ModelSim and Questa, Technical Update.
10:15 - 10:45 Coffee + experts
10:45 - 11:30 Open Verification Methodology - introduction to the concept of open source, standards-based verification methodology.
11:30 - 12:30 Workshop: Practical benefits of
Assertion-based Verification with PSL and SystemVerilog
Constraint Random Verification with SystemVerilog or SystemC
Functional Verification and Coverage
Unified Coverage Database UCDB - Verification Management
Power Aware simulation - Unified Power Format (UPF).
13:30 - 14:30 Workshop: testbench generation with object-oriented programming (OOP) in SystemVerilog and SystemC.
14:30 - 15:15 Clock Domain Crossing verification of complex designs.
15:15 - 15:45 Coffee Break and experts
15:45 - 16:30 Workshop: FPGA with embedded soft processor core: ARM Cortex-M1 as ModelSim / link code verification flow.
16:30 - 17:00 System modeling and simulation in distributed mechatronic systems.
17:00 Price puzzles and adoption

Registration deadline is Wednesday, the 9th April 2008 .