ISVLSI 2008 - IEEE Computer Society Annual Symposium on VLSI - Montpellier, France

Start: Apr 7 2008 - 8:30am

End: Apr 9 2008 - 4:30pm

Timezone: Etc/GMT-8

Where:

Montpellier, France

Event/Conference Information URL:

This Symposium explores emerging trends and novel ideas and concepts in
the area of VLSI. The Symposium covers a range of topics: from VLSI
circuits, systems, design and test methods to system level design and
system-on-chip issues, to bringing VLSI experience to new areas and
technologies. Future design methodologies will also be one of the key
topics at the workshop, as well as new CAD tools to support them. For
almost two decades, the Symposium has been a unique forum promoting
multidisciplinary research and new visionary approaches in the area of
VLSI. It brings together leading scientists and researchers from
academia and industry, and has established a reputation in inviting
well-known international scientists as invited speakers. The 2008
edition will continue to strive to achieve the high standards that
participants have come to expect of this Symposium.

PROGRAMME AT A GLANCE

Monday April 7th
8:30- 9:00		Welcome & Opening Session
9:00- 10:00		Keynote Adaptive Reliable Chips – Reconfigurable Computing in the Nano Era Jürgen Becker, Karlsruhe Institute of Technology – KIT, Germany
10:00-10:50		Session 1-A: Design of Arithmetic VLSI Circuits Session Chair: Ricardo Reis	Session 1-B: Architecture & SoC Design Session Chair: René Cumplido
	10:00-10:25	Arithmetic Data path Optimization using Borrow-Save Representation Sophie Belloeil, Roselyne Avot-Chotin, Habib Mehrez	Benchmarking Domain Specific Processors: A Case Study of Evaluating A Smart Card Processor Design Zhonglei Wang, Thomas Wild, Stefan Rüping, Bernhard Lippmann
	10:25-10:50	Design of Robust and High-Performance 1-bit CMOS Full Adder Omid Kavehei, Mostafa Rahimi Azghadi, Keivan Navi, Amir-Pasha Mirbaha	Determining the optimal Nulmber of Islands in power Islands Synthesis Deniz Dal, Nazanin Mansouri
10:50-11:20		Coffee Break & Poster Session 1
11:20-12:35		Session 2-A: Emerging Technologies Session Chair: Juergen Becker	Session 2-B: Heterogeneous System Design Session Chair: Ian O’Connor
	11:20-11:45	Defect Tolerance Inspired by Artificial Evolution Asbjoern Djupdal, Pauline C. Haddow	Application of Bottom-Up Methodology to RTW VCO Fahd Ben Abdeljelil, Benjamin Nicolle, William Tatinian, Lorenzo Carpineto, Jean Oudinot, Gilles Jacquemod
	11:45-12:10	Reliability of n-Bit Nanotechnology Adder Ismo Hänninen, Jarmo Takala	A Closed-Loop Architecture with Digital Output for Convective Accelerometers Olivier Leman, Frederick Mailly, Laurent Latorre, Pascal Nouet
	12:10-12:35	Spintronics device based Non-volatile Low power SRAM Weisheng Zhao, Eric Belhaire, Claude Chappert, Pascale Mazoyer	A CMOS Multi-sensor System for 3D Orientation Determination Boris Alandry, Norbert Dumas, Laurent Latorre, Frederick Mailly, Pascal Nouet
12:35-14:00		Lunch
14:00-15:40		Session 3-A: Low Power Design I Session Chair: Asim Smailagic	Session 3-B: Multiprocessor SoC Session Chair: Leandro Soares Indrusiak
	14:00-14:25	FSMD Partitioning for Low Power using ILP Nainesh Agarwal, Nikitas Dimopoulos	A Novel Multiple Core Co-Processor Architecture for Efficient Server-based Public Key Cryptographic Applications Ralf Laue, H. Gregor Molter, Felix Rieder, Sorin A. Huss, Kartik Saxena
	14:25-14:50	Uncriticality-directed Low-power Instruction Scheduling Shingo Watanabe, Toshinori Sato	System level design space exploration for multiprocessor system on chip Issam Maalej, Guy Gogniat, Jean Luc Philippe, Mohamed Abid
	14:50-15:15	Smart-NICs: Power Proxying for Reduced Power Consumption in Network Edge Devices Karthik Sabhanatarajan, Ann Gordon-Ross, Mark Oden, Mukund Navada, Alan George	A Novel System-Level On-Chip Resource Allocation Method for Manycore Architectures Theocharis Theocharides, Maria Michael, Marios Polycarpou, Ajit Dingankar
	15:15-15:40	BTB Access Filtering : A Low Energy and High Performance Design Shuai Wang, Jie Hu, Sotirios G. Ziavras	MPI-Based Adaptive Task Migration Support on the HS-Scale System Nicolas Saint-jean, Pascal Benoit, Gilles Sassatelli, Lionel Torres, Michel Robert
15:40-16:10		Coffee Break & Poster Session 1
16:10-17:50		Session 4-A: Low Power Design II Session Chair: Peter Cheung	Session 4-B: System Level Testing Session Chair: Giorgio Di Natale
	16:10-16:35	Low Power High Performance Digitally Assisted Pipelined ADC Bahar Jalali Farahani, Anand Meruva	Process Algebra Based SoC Test Scheduling for Test Time Minimization Jingbo Shao, Guangsheng Ma, Zhi Yang
	16:35-17:00	A Novel Low-Power Clock Skew Compensation Circuit Rong Ji, Liang Chen, Xianjun Zeng, Junfeng Zhang	Improving the test of NoC-based SoCs with help of Compression Schemes Julien Dalmasso, Erika Cota, Marie-Lise Flottes, Bruno Rouzeyre
	17:00-17:25	High Speed Ultra Low Voltage CMOS Inverter Yngvar Berg, Omid Mirmotahari, Johannes Goplen Lomsdalen, Snorre Aunet	A Novel System on Chip (SoC) Test Solution Michael Higgins, Ciaran MacNamee, Brendan Mullane
	17:25-17:50	Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with In-Built Error Detection Avinash Lingamneni, Kirthi Krishna Muntimadugu, Srinivas M B	Testing skew and logic faults in soc interconnects Nestor Hernandez-Cruz, Victor Champac-Vilela
17:50-18:00		Closing & Wrap up of the 1st day
18:00 – 19:30		Cocktail

Tuesday April 8th
9:00- 10:00		Keynote Emerging concepts in non-volatile memory technologies – Era of resistance switching memories Christophe Muller, Ecole Polytechnique Universitaire de Marseille – Université de Provence, France
10:00-10:50		Session 5-A: Hight Performance Circuits Session Chair: Peter Cheung	Session 5-B: Mixed Signal Design Session Chair: Guy Cathebras
	10:00-10:25	A Programmable Frequency Divider in 0.18µm CMOS Library Qingsheng HU, Hua-An Zhao, Chen Liu	Improving Bandwidth while managing Phase Noise and Spurs in Fractional-N PLL Xiao Pu, Axel Thomsen, Jacob Abraham
	10:25-10:50	Energy Recovery from High-frequency Clocks using DC-DC Converters Mehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Shahriar Mirabbasi, William Dunford, Patrick Palmer	Systematic HDL Design of a Delta-Sigma Fractional-N Phase-Locked Loop for Wireless Applications Ahmed El Oualkadi, Denis Flandre
10:50-11:20		Coffee Break & Poster Session 2
11:20-12:35		Session 6-A: Nanoscale Circuits Session Chair: Ian O’Connor	Session 6-B: Telecom & Multimedia Architecture Design and Modeling Session Chair: Michael Hübner
	11:20-11:45	Impact of Technology Scaling on Digital Subthreshold Circuits David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat	A generic design for encoding and decoding variable length codes in multi-codec video processing engines V.K.Prasad Arava, Manhwee Jo, Hyouk Joong Lee, Kiyoung Choi
	11:45-12:10	Low Standby Power and Robust FinFET Based SRAM Design Behzad Ebrahimi, Saeed Zeinolabedinzadeh, Ali Afzali-Kusha	Transforms and Quantization in the High-Throughput H.264/AVC Encoder Based on Advanced Mode Selection Grzegorz Pastuszak
	12:10-12:35	CMOS Control Enabled Single-Type FET NASIC Pritish Narayanan, Michael Leuchtenburg, Teng Wang, Csaba Andras Moritz	Communication Centric Modelling of System on Chip Devices Targeting Multi-Standard Telecommunication Applications Ali Ahmadinia, Balal Ahmad, Tughrul Arslan
12:35-14:00		Lunch
14:00-15:40		Session 7-A: Physical Design Session Chair: Michel Robert	Session 7-B: Test & Verification Session Chair: Bruno Rouzeyre
	14:00-14:25	Performance Improvement of Physical Retiming with Shortcut Insertion Adel Dokhanchi, Mostafa Rezvani, Ali Jahanian, Morteza Saheb Zamani	A Real Case of Significant Scan Test Cost Reduction Selina Sha, Bruce Swanson
	14:25-14:50	A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation Yibo Wang, Yici Cai, Xianlong Hong	A Network Based Functional Verification Method of IEEE 1394a PHY Core Colin Yu Lin, Song Cao, Junshe An, Fei Han, Qifei Fan
	14:50-15:15	A Buffer Sizing Methodology for Clock Meshes for Skew and Power Reduction Gustavo Wilke, Ricardo Reis	Cohesive Coverage Management for Simulation and Formal Property Verification Aritra Hazra, Ansuman Banerjee, Srobona Mitra, Pallab Dasgupta, Partha Pratim Chakrabarti, Chunduri Rama Mohan
	15:15-15:40	An efficient method to estimate crosstalk after placement incorporating a reduction scheme Arash Mehdizadeh, Morteza Saheb Zaman, H. Shafiei	Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors Ilia Polian, Sudhakar Reddy, Bernd Becker
15:40-16:10		Coffee Break & Poster Session 2
16:10-17:50		Session 8-A: Models for low Power Design Session Chair: Ann Gordon Ross	Session 8-B: Dynamic Reconfiguration Management Techniques Session Chair: Guy Gogniat
	16:10-16:35	Memory Power Modeling - A Novel Approach Ajit Gupte, Mohit Sharma, Gaurav Varshney, Lakshmikantha Holla, Parvinder Rana, Udayakumar H	Core allocation and relocation management for a self dynamically reconfigurable architecture Massimo Morandi, Marco Novati, Marco Domenico Santambrogio, Donatella Sciuto
	16:35-17:00	Integrated Power-Gating and State Assignment for Low Power FSM Synthesis Sambhu Nath Pradhan, M.Tilak Kumar, Santanu Chattopadhyay	SeReCon : a Secure Dynamic Partial Reconfiguration Controller for SoPCs Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Tomasz Surmacz
	17:00-17:25	Efficient High-Level Power Estimation for Multi-Standard Wireless Systems Ali Ahmadinia, Balal Ahmad, Tughrul Arslan	GePaRD - a High-Level Generation Flow for Partially Reconfigurable Designs Maik Boden, Markus Reiband, Thomas Fiebig, Peter Reichel, Steffen Rülke, Jürgen Becker
	17:25-17:50	Modeling and Optimization of Switching Power Dissipation in Static CMOS Circuits Adnan Kabbani	Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs Katarina Paulsson, Michael Hübner, Ulrich Viereck, Jürgen Becker
17:50-18:00		Closing of the 2nd day
20:00		Social Event - Opera Comedie

Wednesday April 9th
8:30- 9:15		Invited Industrial Presentation From in-Silicon to in-Situ test Philippe Cauvet, NXP, France
9:15-10:55		Session 9-A: Hot Topic : Variability-Insensitive Design Techniques Session Chair: Lionel Torres	Session 9-B: Network On Chip Session Chair: Gilles Sassatelli
	9:15-9:40	Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects Michael yap san min, Philippe Maurine, Magali Bastian, Michel Robert	Flow Maximization for NoC Routing Algorithms Ying-Cherng Lan, Michael Chen, Alan Su, Yu-Hen Hu, Sao-Jie Chen
	9:40-10:05	Setup and Hold Timing Violations induced by Process Variations, in a Digital Multiplier Bettina Rebaud, Zequin Wu, Marc Belleville, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azemard	Deadlock-Free Multicast Routing Algorithm for Wormhole-Switched Mesh Networks-on-Chip Everton Carara, Fernando Moraes
	10:05-10:30	Characterisation of FPGA Clock Variability Pete Sedcole, Justin Wong, Peter Cheung	Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques Julian J. H. Pontes, Matheus T. Moreira, Rafael I. Soares, Ney L. V. Calazans
	10:30-10:55	A Fuzzy Optimization Approach for Process Variation Aware Buffer Insertion and Driver Sizing Mahalingam Venkataraman, Nagarajan Ranganathan
10:55-11:25		Coffee Break
11:25-12:40		Session 10-A: VLSI Circuits Session Chair: Amar Mukherjee	Session 10-B: Hot Topic : Temperature-aware Design Session Chair: Fernando Gehm Moraes
	11:25-11:50	Adaptive Neuron Activation Function with FGMOS Based Operational Transconductance Amplifier V. Suresh Babu, Rose Katharine A.A, M. R. Baiju	Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki Murakami
	11:50-12:15	A Versatile Linear Insertion Sorter Based on a FIFO Scheme Roberto Perez-Andrade, Rene Cumplido, Fernado Martin del Campo, Claudia Feregrino	Thermal-aware Placement of Standard Cells and Gate Arrays: Studies and Observations Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta
	12:15-12:40		Temperature-Aware Distributed Run-Time Optimization on MP-SoC using Game Theory Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres
12:40-14:15		Lunch
14:15-15:55		Session 11-A: Reconfigurable-based Circuits & Methods Session Chair: Michael Huebner	Session 11-B: System Level Design & Tools Session Chair: Ali Ahmadinia
	14:15-14:40	Standard Cell Like Via-Configurable Logic Block for Structured ASIC Mei-Chen Li, Hui-Hsiang Tung, Chien-Chung Lai, Rung-Bin Lin	Petri Net based rapid prototyping of digital complex David Andreu, Guillaume Souquet, Thierry Gil
	14:40-15:15	SDVM-R: A Scalable Firmware for FPGA-based Multi-Core Systems-on-Chip Andreas Hofmann, Klaus Waldschmidt	Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler
	15:15-15:30	Fast Hardware Upper-Bound Power Estimation for a Novel FPGA-Based HW/SW Partitioning Scheme Mohamed B. Abdelhalim, Serag E.D. Habib	A Multi-Objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis Fabrizio Ferrandi, Pier Luca Lanzi, Daniele Loiacono, Christian Pilato, Donatella Sciuto
	15:30-15:55	FPGA-Based Circuit Model Emulation of Quantum Algorithms Mahdi Aminian, Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi	Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis Hariharan Sankaran, Srinivas Katkoori
15:55-16:15		Closing Session - Best paper award