Electronic Design Processes (EDP) 2008 - MONTEREY, CALIFORNIA

Start: Apr 16 2008 - 5:30pm

End: Apr 18 2008 - 6:30pm

Timezone: Etc/GMT-8

Where:

MONTEREY BEACH HOTEL, MONTEREY, CALIFORNIA

Event/Conference Information URL:

The Electronic Design Processes (EDP) Workshop provides a forum for a cross-section of the design community to discuss state-of-the-art electronic design processes and CAD methodologies. The workshop focuses on the improvement of the overall design process, rather than on the functions of the individual tools themselves.

EDPS 2008 Preliminary Workshop Program:

Speaker	Affiliation	Title/Area of Talk
Wednesday, April 16, 2008
Registration
05:30-7:00 PM Evening Reception @ Captain’s Table
Thursday, April 17, 2008
08:30 AM - 09:10 AM Welcome Host: Patrick H. Madden, SUNY Binghamton
Keynote Address Timothy G. Mattson / Intel Parallel Computing: Can We Please Do it Right?
Session: Embedded Microprocessor Design Session Chair: TBD
Grant Martin, Steve Leibson	Tensilica	Embedded Boot Camp: AMP vs. SMP
Radhika Thekkath	MIPS	Max Out Your Multi's
Ian Rickards	ARM
Ray Brinks	Sonics Inc.	Microprocessor Centric SoC's are Dead
Akash Deshpande	ARC	Solutions for SoC Design
Session: EDA Standards Panel Session Chair and Organizer: John Darringer (IBM)
John Darringer	IBM
Gary Delp, Technical Director	SPIRIT
Jake Buurma and Steve Schulz, President	SI2
Victor Berman, Chairman	IEEE DASC
Rohit Kapur, Chairman	IEEE TTSC
Session: Manufacturing Challenges and Solutions Session Organizer: TBD
Puneet Gupta	UCLA/Blaze
Andres Torres	Mentor Graphics	Regular Designs and Computational Lithography: Their Past, Present, and Future
Bhanu Kapoor, Auturo Salz, Shankar Hemmady	Mimasic/Synopsys	Multi-Voltage Power Managment Verification Issues
Srivasta Vasudevan	Synopsys	Verification Minimization with Karnaugh Maps
Session: Nuts and Bolts of EDA Tools Session Chair: TBD
Patrick Groeneveld	Magma	TCL as an EDA tool flow integrator: the good, the bad, and the ugly.
Joao Gaeda	CLKda	Efficient Use of Multicore Processors for Timing Analysis
Igor Markov	U Michigan	On Libraries, Reuse, and the Value of EDA Software
EDP Banquet Dinner Panel Discussion on EDA and the Industry Press Richard Goering, SCDsource Gabe Moretti, GabeOnEDA
Friday, April 18, 2008
Session: EDA Venture Capital Outlook
Juan-Antonio Carballo	Argon VC

Session: Standardization and Virtualization
Aman Joshi	Director of IC Tools, Sun Microsystems	OpenSparc
Larry Lapides	Imperas	Open Virtual Platforms
Michel Genard	Virtutech	Virtualized Software Development
Sessions: ESL and High Level Design Session Organizer: TBD
Rajesh Gupta	UC San Diego	The Next EDP Challenge: Cost of ASIC Design & Validation
Rishiyur Nikil	Bluespec	Using Parallel Atomic Transactions in SoC Design
Alec Stanclescu	FinTronic
Session: Renewing and Educating on IEEE on Design Standards Processes Session Organizer: Alec Zamfirescu
TBD
Closing Remarks