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Cadence Event / Pebble Beach Party System-Level Verification -San Jose, CA
This techtorial will cover the Cadence system level verification technology using a customer's example. Through lectures, industry speakers, and case studies, this techtorial will help you understand and drive the latest products and flows that constitute a Cadence system level verification methodology.
Featuring Methodologies and Techniques Utilizing:SystemC simulation, transaction-level modeling, transaction-based acceleration, in-circuit emulation, acceleration of constrained-random coverage driven verification, and hardware / software co-verification.
Key items detailed in this techtorial include:
- Transaction-level modeling
- Transaction-based acceleration
- In-circuit emulation
- Acceleration of constrained-random coverage driven verification
- SystemC Simulation
- Hardware / Software co-verification
Agenda:
9:30am -10:00am Registration/Breakfast
10:00am - 10:30am Industry Challenges by Keynote Speaker
John Goodenough - ARM,MethodologyDirector
10:30am - 11:15am Cadence High Speed Simulation & Advanced Verification Techniques
11:15am - 12:00pm Using Coverage-Driven Verification to Automate Hardware/Software Co-verification
12:00pm - 12:30pm Hardware / software co-verification case studies. Speaker: Vijay Meduri - PLX Tech., R & D Director
12:30pm - 1:30pm Lunch & Special topic
Speaker: Brian Bailey - Accellera ITC Committee Chairman, ESL Consultant
FPGA Webcasts
Upcoming FPGA Events
- The Fourth Annual Reconfigurable Systems Summer Institute (RSSI'08) - Urbana, IL(Event or Conference)(2 days)
- AVMS VI-01: An Introduction to Transaction Level Modeling in SystemC(Event or Conference)(5 days)
- ENGINEERING OF RECONFIGURABLE SYSTEMS AND ALGORITHMS - ERSA’08 - Las Vegas, Nevada(Event or Conference)(9 days)
- AVMS VI-02: Practical Examples of PSL Usage(Event or Conference)(12 days)
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