Prototyping: Easing the Transition from ASIC to FPGA Design - San Jose, CA

Agenda:

1. The need for ASIC prototyping with FPGAs
1. Using FPGAs for verification
2. Choosing the right FPGA
2. Making a smooth transition from ASIC design to FPGA design
1. Selecting a design flow
2. Considerations for technology specific cells
3. Verifying the same ASIC code and constraint proves more value in the emulation process
3. Debugging and analysis of the prototype design
1. Design analysis and cross-probing the FPGA and the RTL
2. Making design changes efficient
4. Making decision in Synthesis to improve performance
1. Timing analysis
2. Resource management
3. Performance enhancements for timing and area

Seating is VERY limited to maximize your learning experience, so submit your interest immediately to request your spot. Lunch and refreshments will be provided.