EDA Tech Forum - Boston, MA

October 18, 2007
9:00 - 9:50 Breakfast/Registration/Vendor Fair
10:00 - 10:50 Keynote: Dances with Robots: The Story of One Engineer, 112 Little Robots, and the Toys, Insects, and Star Wars Movies that Made it all Possible
11:00 - 11:50 Technical Sessions (Choose below)
12:00 - 2:00 Lunch/Vendor Fair
2:00 - 2:50 Technical Sessions (Choose below)
3:00 - 3:50 Technical Sessions (Choose below)
4:00 - 4:50 Technical Sessions (Choose below)
5:00 - 6:30 Cocktail Reception/Prize Giveaway

Choose Your Sessions

Create your schedule by selecting the sessions you would like to attend.
PCB Symposium
11:00 - 11:50 Managing Industry Trends: Successful PCB Design with Today's High-Speed Architectures [ Show abstract ]

In this presentation, we will examine the current trends in high-speed bus architectures, including parallel busses such as DDR2 as well as SERDES busses such as PCI-Express. The design requirements created by these architectures will be thoroughly examined, in addition to the tools and techniques necessary to overcome design challenges.
2:00 - 2:50 Implementing SERDES Busses: A Formidable High-Speed Design Challenge [ Show abstract ]

With edge rates of new SERDES busses such as PCI Express, Serial ATA, and FibreChannel entering into the sub-100ps range, utilizing the proper design technology is vital to success. In this 1-hour presentation, we will discuss the needs set forth by today's Gigabit-speed busses, and thoroughly explore the analysis techniques to ensure their proper operation. Differential signalling, eye diagrams, S-parameters, bit error rate, and loss will all be explained and their relevance to SERDES design discussed in detail.
3:00 - 3:50 Advanced Routing Technologies [ Show abstract ]

Electronic companies today are competitively driven to produce higher complexity products, at cheaper costs in less time. A significant percent of the design cycle time is spent routing the PCB either manually or with the aid of an autorouter to produce the densest and highest performing result. This session will discuss new and innovative approaches to the routing process including technologies that are unique and patented by Mentor Graphics. These technologies are giving users up to a 50% improvement in productivity and design cycle time.
4:00 - 4:50 Design for PCB Manufacturing [ Show abstract ]

Including design-for-manufacturing functionality and checking in the design process, rather than waiting for the manufacturer to discover errors, can significantly reduce design cycle times as well as insure the lowest production costs. This session will discuss design process rule setup, design for fabrication checking, communication to manufacturing during the design process, and manufacturing data preparation.
Chip Symposium - Track A
11:00 - 11:50 Developing ARM Cortex-M1 Processor Based Embedded Systems for FPGA. Presented by ARM. [ Show abstract ]

The recently-announced ARM Cortex-M1 processor is the first ARM processor optimised for synthesis on FPGA, bringing the benefits of the broad ARM ecosystem and compatibility. In this session we will present an introduction to the ARM Cortex-M1 processor, and how systems can be rapidly developed and implemented using comprehensive solution offerings from the ARM Connected Community.
2:00 - 2:50 Efficient Full-chip Mixed-signal Verification by Leveraging Fast-SPICE Technology [ Show abstract ]

Large mixed-signal system-on-chip designs, blending complex analog and digital blocks, require thorough testing with the right mixed-signal verification tool. The ADVance MS mixed-signal simulator offers comprehensive technologies that support multiple modeling languages: VHDL, Verilog, VHDL-AMS, Verilog-AMS, SystemC, SystemVerilog, and SPICE. A new fast-SPICE simulation technology, ADiT, has been introduced into ADVance MS platform. The ADiT engine is specialized in robust and accurate simulation for analog and mixed-signal circuits; therefore, it is the perfect fast-SPICE engine to complement ADVance MS. With this fast-SPICE technology, mixed-signal SoC with large analog and mixed-signal circuits in transistor level can be validated accurately and efficiently.
3:00 - 3:50 Practical Applications of Mentor's Advanced Verification Methodology [ Show abstract ]

While many engineers understand the concepts of new verification techniques, they may be unsure of how best to apply them to their particular project. Mentor Graphics Advanced Verification Methodology (AVM) was developed explicitly to help verification teams get past this "blank page" phase of the project by providing a library of modular, reusable transaction-level verification components to efficiently create transaction-level testbenches for today’s advanced technologies: constrained-random stimulus, functional coverage, and assertions. This session provides an overview of transaction-level modeling (TLM) and the AVM for planning and analysis, including how to develop testbenches for real-world applications. A demonstration encapsulating the testbench for reusability and customization is also included in this presentation.
4:00 - 4:50 Blended Coverage – A Recipe for Success [ Show abstract ]

Verification, like an exotic blender concoction, is a multi-dimensional undertaking that generally spans multiple levels of abstractions, evolves throughout a project’s lifecycle, and depends on multiple tools and processes. Success requires coverage metrics to determine the quality and completeness of the verification process, and serve two primary purposes: 1) Identify where we have been (that is, what functionality or implementation structures have been verified), and 2) Identify how far we have to go (that is, where the verification process currently stands in terms of completion). Yet measuring and analyzing coverage, like verification itself, is a multi-dimensional problem—whose recipe for success requires a skill in the art of managing and merging multiple views of data from multiple heterogeneous tools. With the emergence of recent standards, such as the IEEE Std-1800 SystemVerilog, many verification teams are starting to integrate advanced coverage-driven verification techniques into their flows. Some teams focus entirely on manually specified functional coverage techniques—other teams focus on automatically extracted structural coverage techniques, while others blend the multiple techniques to identify holes in their coverage model. This session offers a perspective of today’s coverage problems, including best approaches for blending coverage.
Chip Symposium - Track B
11:00 - 11:50 The Evolving Role of Sign-Off [ Show abstract ]

A firestorm has ignited in the semiconductor industry over how IC design tools and methodologies should evolve to address the challenge of achieving yield in nanometer technology. Part of the debate centers on physical verification where there is clearly a need for a rethinking of the process. Without a significant change in the physical verification process, a dramatic increase in total cycle time, driven by Moore's Law, more design rule checks, and longer debug times promises to wreak havoc. The days of relying on ‘DRC clean’ results to ensure yield is also a thing of the past. Today, EDA vendors are hard at work extending the range of tools supporting sign-off to meeting the changing landscape introduced with the nanometer age. In this session you will hear about how DRC steps now incorporate statistical yield modeling, rather than just threshold comparisons. In addition to a fundamental DRC change, Layout database characteristics can now be extracted and represented as statistical distributions. Designers gain insight into the range of results in comparison to both compliance thresholds and recommended rule values. Yield models applied to these results prioritize them by providing the designer with a design quality score. Finally, new visualization tools allow a designer to select the highest priority result and work on it in his preferred layout environment.
2:00 - 2:50 Proven Strategies for Integrating DFM Technologies [ Show abstract ]

A key factor in attaining acceptable yield levels is understanding and accounting for the interaction between design and manufacturing. Yield losses in the newer processes include random, systematic and parametric defects and issues with testing. Each of these sources of yield loss needs to analyzed and understood by designers and tool developers. In addition, new techniques and methods must be devised to minimize the impact of these yield loss mechanisms. This session describes the Mentor Graphics tools and methodologies that address critical area analysis, recommended rule analysis, lithographic simulation and the importance of foundry support for these tools.
3:00 - 3:50 Leveraging a Cross-foundry DFM Approach to Maximize 65nm. Presented by Common Platform Group [ Show abstract ]

Tight collaboration between foundries and EDA/DFM suppliers is critical to increase ‘manufacturing awareness’ earlier in the design cycle. By jointly developing methodologies based on information sharing and tool optimization for specific processes, foundries and EDA companies allow mutual customers to analyze their designs for manufacturability, identify possible yield detractors, and perform the appropriate trade-offs to take the relevant actions. This session presents the types of tools and data that can more effectively address manufacturability early on to achieve first time right silicon, faster production ramp times, and higher yields. Also addressed are tools and approaches to deal with pressing design closure challenges, such as timing, area, power, and signal integrity. It includes an overview of a robust DFM solution consisting of a series of rules- and model-based design kits that allow designers to better predict the impact their decisions will have on a manufactured designs implemented in a variety of operating ranges, modes, and conditions. Three of the world’s leading semiconductor companies -- IBM, Chartered Semiconductor Manufacturing and Samsung -- have taken the concept of foundry/DFM supplier cooperation to a new level, with a unique collaboration to jointly develop and support leading-edge manufacturing capabilities in their respective foundries. Find out more about the Common Platform technology approach to design at 90nm, 65nm and 45nm, and how to leverage a comprehensive DFM platform that includes all the necessary information to target the same design at all three fabs.
4:00 - 4:50 Change Under Our Feet: Why 100x Test Compression is the New Scan Test Standard [ Show abstract ]

The arrival of the 90 nm technology node has significantly changed testing requirements. Growing circuit sizes and new defect mechanisms have thrust compression into the mainstream of test pattern development. Learn from the experts how compression is being applied to today's designs, and how this technology will meet the requirements of tomorrow's smaller geometries.
Chip Symposium - Track C
11:00 - 11:50 Achieving Optimal Designs Through Electronic System Level (ESL) Methodologies [ Show abstract ]

Today’s advanced designs have grown too massive and complex to cost-effectively design and verify using traditional RTL methodologies alone. This trend toward increasing complexity has led to more ASIC re-spins, lost revenue from missed design deadlines, and sub-optimal systems that are larger, slower or consume more power than required. Electronic System Level (ESL) design methodologies address this complexity problem by elevating design to a higher level of abstraction. This relieves hardware designers from the design errors caused by the overwhelming detail of lower-level methodologies. Even more important, the single source methodology eliminates the most common source of errors between the system designer and the hardware designer. In this session, attendees will learn how to use SystemC transaction-level modeling (TLM) to quickly perform architectural tradeoffs for power, performance and area, and evaluate hardware/software interactions. Attendees will also learn how best-in-class high-level synthesis technology can support TLM-based processes, and automate the creation of optimized RTL implementations while allowing designers to easily target interface protocols for buses or memory components – all without changing the source code. Using this methodology, designers can create, optimize and verify designs that are tailored to their design specifications 10-100X more productive than traditional methodologies.
2:00 - 2:50 Model-based Design and System-level Functional Verification. Presented by The MathWorks. [ Show abstract ]

Using real-world signal processing application examples, this presentation will illustrate how Model-Based Design accelerates the design and implementation of complex algorithms in FPGAs and ASICs. MathWorks engineers will discuss the complete development flow including floating-point algorithm development, refinement to include finite wordlength effects; executable specification and system simulation; automatic generation of synthesizable HDL and system-level testbenches; integration of optimized HDL; and system-level functional verification using Simulink product family with HDL simulators such as Mentor’s ModelSim.
3:00 - 3:50 An Integrated Design Flow for FPGA Design and ASIC Prototyping [ Show abstract ]

The latest generations of FPGAs — offering greater logic densities, more memory, specialized embedded functions, and reduced cost — open up new applications for FPGAs. But this greater applicability puts greater requirements on the design flow — push-button flows are often not sufficient. What designers need today is a flow that can be configured to the specific needs of the design task, whether it is a traditional FPGA design, a complex system on a chip involving DSP and high-speed serial communication, or for ASIC prototyping. This session will cover how Mentor Graphics FPGA design tools can be tailored to your needs, allowing you to get the most out of today’s newest FPGAs.
4:00 - 4:50 Optimizing System Design Using FPGA. Presented by Lattice Semiconductor. [ Show abstract ]