Lattice High Speed Interface Speedway Design Workshop - San Jose, CA

This speedway is an opportunity for engineers to become acquainted with emerging high speed interface techniques that will enable them to implement new designs using these state of the art interfaces, topics include:

SERDES:
Applications, usage, and design challenges such as clock management will be covered.

PCI-e:
Bus architecture, implementation, and design techniques such as PCB layout, and hot swap power management will be covered.

DDR2:
Usage, implementation, and additional topics such as PCB layout, and signal termination.

All these technologies will be demonstrated using the latest in FPGA technology from Lattice allowing engineers to accelerate their new designs.

Cost:
$149

Agenda
8:00-8:30 Registration
8:30-9:15 SERDES 101
9:15-10:45

Lab 1 & 2

* ispLever Introduction
* ipExpress Introduction
* SERDES IP
* SERDES Demonstration

11:00-12:00 PCI-e Architecture
12:00-12:30 Lunch
12:30-1:00 PCI-e Design Considerations

1:00-2:00

Lab 3

* PCI-e IP
* PCI-e Demonstration

2:15-3:00 DDR2 Design Considerations
3:00-4:00

Lab 4

* DDR2 IP
* DDR2 Demonstration