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Power Implications of Implementing Logic Using FPGA Embedded Memory Blocks
September 10, 2008 - 4:03pm — scottcOn-chip user memory has become a common resource on modern FPGAs. This memory comes in the form of configurable Embedded Memory Blocks (EMB). EMBs are very area efficient for implementing designs
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Cadence Open Verification Methodology (OVM) Technical Seminar - San Jose, CA
* Learn how an open SystemVerilog methodology can be leveraged across teams, projects, and platforms
* Understand the architecture behind reusable verification IP and environments
* View the class library and find out how you can use it
* See a live demo of the OVM and talk with methodology experts
Get your OVM questions answered—this is a must-attend seminar for design and verification teams. Register today!
Agenda
8:30am Continental Breakfast and Registration
9:30am Keynote: The Power of Open – SystemVerilog Methodology
10:00am Achieving SystemVerilog Language and Platform Interoperability
10:30am Building Reusable SystemVerilog Verification Environments
11:00am BREAK
11:15am Panel: Delivering on the SystemVerilog Promise for Design and Verification Teams
12 noon LUNCH
1:00pm OVM Across Design and Verification Teams
1:45pm OVM Demo
2:15pm Closing Remarks
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