World's 1st FPGA/CPLD Portal

As FPGA density and I/O pin counts continue to increase, it becomes
imperative for FPGA, System, and PCB designers to work together. Only
as a team, can design time and production costs be minimized and
maximum system performance achieved.

No longer can companies focus solely on FPGA design goals while
disregarding the issues that pin assignments create for PCB routing and
performance. Conversely, companies cannot focus solely on PCB layout,
as over-constrained layouts will create problems for FPGA
place-and-route tools, making it difficult to achieve timing closure.

With I/O Designer, engineers from multiple disciplines can
collaborate in a common environment to create FPGA pin assignments
optimized for the entire system. This seminar will include an
introductory presentation on the theory of FPGA/PCB integration
followed by a demonstration of I/O Designer in a PCB design flow.