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Mid-Atlantic Region Local Users Group (MARLUG) - Laurel, MD

When: 
Oct 10 2007 - 4:00pm
Where: 
John Hopkins University Applied Physics Laboratory (APL), Laurel, MD

Agenda

Keynote:
Technology Leadership through Innovation – Meeting the Challenges
Wednesday, October 10 • 9:00am – 10:00am
Henry Potts, General Manager: Systems Design Division, Mentor Graphics

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Go Green: Conserve Energy and Find it Fast on New SupportNet
Wednesday, October 10 • 3:00pm – 4:00pm
Christine Egli, Worldwide Customer Support Web Director, Mentor Graphics

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SI/CES/AutoRouting
Wednesday, October 10 • 11:00am – 12:00pm
Ned Dempsher, Signal Integrity Expert, L-3 Communications
Ted Lin, Applications Engineer, Mentor Graphics

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TBD
Wednesday, October 10 • 1:00pm – 2:00pm

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Board Station XE: The Next Generation Design Flow
Wednesday, October 10 • 2:00pm – 3:00pm
Steve Shively, Board Station XE Product Marketing Manager, Mentor Graphics

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Tips & Tricks with PADS & High-Speed
Wednesday, October 10 • 11:00am – 12:00pm
Ernie Frohring, Senior Applications Engineer, Trilogic

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Integrating the Common CAD Library with a Global Enterprise System using the Dx-PADS Workflow
Wednesday, October 10 •1:00pm – 2:00pm
Ed Turngren, CAD Manager, Andrew Corporation

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PADS Product Update
Wednesday, October 10 • 2:00pm – 3:00pm• Jim Oakley, Technical Marketing Engineer, Mentor Graphics

General:
Macrovision’s FLEXNet – Hype or Hope?
Wednesday, October 10 • 10:00am – 11:00am
Rachel Stanley, License Administrator, Honeywell

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TBD
Wednesday, October 10 • 11:00am – 12:00pm

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Customizing your Search with the MGC Documentation System
Wednesday, October 10 • 1:00pm – 2:00pm
Sarah Leritz-Higgins, Senior Technical Writer, Mentor Graphics

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TBD
Wednesday, October 10 • 2:00pm – 3:00pm

High-Speed:
The High-Speed Serial link Designers Survival Guide
Wednesday, October 10 • 9:00am – 10:00am
Eric Bogatin, Signal Integrity Evangelist, Bogatin Enterprises
Presented by: Pat Carrier, Technical Marketing Engineer, Mentor Graphics

In this session, we will review the 4 interconnect problems in high-speed serial links and what can be done to minimize the hit from the interconnect. The four problems are: losses, reflections, intra-line skew and cross talk.

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Batch Mode and Multi-Board Simulations
Wednesday, October 10 • 10:00am – 11:00am
Alex Golian, Northrop Grumman

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HyperLynx
Wednesday, October 10 • 1:00pm – 2:00pm
Bob Hendrick, Altera

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High-Speed Product Update
Wednesday, October 10 • 2:00pm – 3:00pm
Pat Carrier, Technical Marketing Engineer, Mentor Graphics

IC-ASIC:
Enabling MPRUN in Eldo/ADMS -- Problems and Solutions
Wednesday, October 10 • 9:00am – 10:00am
Abhishek Bhaduri, CAD Engineer, Cypress Semiconductor

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Fast ECO Closure using Calibre
Wednesday, October 10 • 10:00am – 11:00am
Rajesh Bansel, Freescale
Priyanka Bhan, Freescale

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TBD
Wednesday, October 10 • 1:00pm – 2:00pm

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TBD
Wednesday, October 10 • 2:00pm – 3:00pm

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