User login

AVMS VI-01: An Introduction to Transaction Level Modeling in SystemC

Jul 10 2008 - 11:00am
Jul 10 2008 - 12:00pm
Etc/GMT-8
Where: 
Online Webinar, Thursday 7/10/2008, 11:00 AM (Pacific Daylight Time)

Presenter: Doulos

Abstract: The OSCI transaction-level modeling working group has recently completed the new TLM 2.0 standard for modeling bus-based systems with SystemC. This builds on the TLM 1.0 standard (released in 2004). This presentation introduces the main features of both standards and shows how they can be applied to model a typical memory-mapped bus at various levels of abstraction.

Agenda:

• Why Transaction Level Modeling?
• Overview of TLM1.0 and TLM2.0 standards
• Creating a SystemC model of a memory-mapped bus-based system

Average rating
(0 votes)

Upcoming FPGA Events