PlanAheadÃƒÂ¢Ã¢â‚¬Å¾Ã‚Â¢ delivers a faster, more efficient FPGA design solution to help achieve your performance goals.
PlanAhead streamlines the design step between synthesis and place and route. The result is a significant reduction in both the number and the length of design iterations. This methodology allows designers to divide a larger design up into smaller, more manageable blocks and focus efforts toward optimization of each module, improving performance and quality of the entire design.
(1) PinAhead - PinAhead provides fully automatic or semi-automated assignment of I/O ports to physical package pins.
(2) ExploreAhead - ExploreAhead, integrated within PlanAhead, is an implementation exploration tool. By managing multiple implementation runs, ExploreAhead allows the user to execute multiple implementation runs based on strategies theyÃƒÂ¢Ã¢â€šÂ¬Ã¢â€žÂ¢ve defined or predefined strategies shipped as factory defaults.
(3) Signal Integrity - PlanAhead provides functionality to check limits for Weighted Average SSO (WASSO) analysis. This allows designers to more easily limit the amount of ground bounce present immediately at the output of the FPGA and prevent corruption of the operation of other devices driven by the FPGA.
(4) Partial Reconfiguration - PlanAhead simplifies the powerful, yet complex, design flow for partial reconfiguration. Partial reconfiguration is a unique method of changing a dynamic portion of a design while the static portion continues to operate. Partial reconfiguration allows you to reduce the size, weight, cost and power of your design. Users interested in exploring the benefits of Partial Reconfiguration are encouraged to contact their local Xilinx FAE.
(5) TimeAhead - TimeAhead is a flexible timing analyzer integrated into PlanAhead. It allows you to estimate route delays before running place and route. Using the PlanAhead block-based approach, the accuracy of timing estimates will improve as blocks in the design are implemented through place and route.