Planet FPGA
- Tired of dealing with rogue software, spyware, and malware?
- Visual Enhancement Engine (VEE) evaluation module from QuickLogic
- Massively parallel processing arrays (MPPAs) for embedded HD video and imaging (Part 1)
- Virtualization Moves Onto Custom Microcontroller
- Samplify announces compression for tomography
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AccelDSP Synthesis Tool
AccelDSP™ Synthesis Tool is a high-level MATLAB® language based tool for designing DSP blocks for Xilinx FPGAs. The tool automates floating- to fixed-point conversion, generates synthesizable VHDL or Verilog, and creates a testbench for verification. You can also generate a fixed-point C++ model or System Generator block from a MATLAB algorithm. AccelDSP synthesis tool is a key component of the Xilinx XtremeDSP™ solution that combines state-of-the-art FPGAs, design tools, intellectual property cores, and partnerships, as well as design and educational services.
Device Family Support
Spartan™-3A DSP
Spartan-3A, AN
Spartan-3
Spartan-II, IIE
Virtex™-5 SXT
Virtex-5
Virtex-4
Virtex-II Pro
Virtex-II
Virtex /E/EM
Key Features:-
(1) DSP modeling – Design, architectural exploration, and debug of high-level DSP algorithms with MATLAB for Xilinx FPGAs to reduce design cycles and costs.
(2) IP-Explorer Technology – Heuristic-driven selection of hardware architecture at the algorithmic level to produce system-optimized designs.
(3) Automated floating- to fixed-point conversion – Automated word width selection and propagation for floating- to fixed-point conversion.
(4) Automatic code generation of synthesizable VHDL or Verilog – Bit-accurate code generated after fixed-point design meets system specifications.
(5) Verification of bit-accuracy – Comparison of RTL and post-place and route model for automatic verification.
(6)C++ simulation model generation – Improved simulations speeds of 1000x over standard fixed-point MATLAB.
(7) System Generator integration – Generated blocks can be exported to System Generator for inclusion in a larger system.
(8) Third party integration – Access to and integration of third party simulation and synthesis tools to simplify the design flow for algorithm designers unfamiliar with RTL simulation and synthesis tools.
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