Poll

What is your preferred platform for FPGA Design Flow ?:

Identify Pro

EDA Tool Vendor: 
Synplicity, Inc.

The Identify Pro software, featuring Synplicity’s TotalRecall™ technology, provides designers with full visibility into complex FPGA and FPGA-based ASIC prototypes enabling them to find bugs at hardware speed and debug the cause of errors in a familiar simulation environment. Identify Pro software works complementary to other verification methodologies, such as assertion-based verification and simulation significantly improving the overall productivity.

Sometimes errors in a design manifest themselves only when the design is running with the rest of the system components in a real world environment. In other cases, the bugs may occur infrequently or in a non-deterministic manner. The Identify Pro software adds advanced triggering and full visibility to FPGA-based prototyping systems, thus making it feasible to detect these hard-to-find bugs. Upon occurrence of the error condition, Identify Pro software creates the necessary simulation environment including a test bench, so that the bug can be analyzed, fixed and verified in a RTL simulation environment. The Identify Pro tool allows a user to capture the logic state and the input sequence to the design in hardware just prior to a failure and then simulate and replay the error condition using a standard RTL simulator.

EDA Tool Category: 
Debugging

Identify Pro Product Benefits:-

Full Visibility into The Design Under Test -
When a functional bug or assertion failure occurs, the state values of all registers and all memory contents are captured prior to the trigger being reached for a user-defined number of clock cycles. The Identify Pro software not only captures the complete state of the design under test at the instant when the trigger occurs but also the sequence of inputs leading to the occurrence of the bug, all of which is typically cumbersome in a traditional verification environment.

RTL Source Code Debug -
The Identify Pro tool uses a patented technology to insert instrumentation and to enable debugging within the RTL source code. It uses advanced sample and triggering capabilities directly in the RTL including the ability to use assertions as triggers.

Automatic Test Bench Generation -
One of the most powerful capabilities in the Identify Pro software is to automatically create a test bench suitable for a standard RTL simulator. Once the bug occurs in the hardware, the state and the input sequence to the design are captured and stored for a user defined number of cycles leading up to the occurrence of the bug. The TotalRecall technology automatically formats the input stimulus sequence to run on a RTL simulator of choice. At this point you can simulate and replay the error condition in the RTL simulator.

Assertion Synthesis And Assertion Debug -
The TotalRecall technology within the Identify Pro software allows the designer to use the same assertions as in the RTL simulation. These assertions are synthesized and mapped into the hardware device, FPGA, or ASIC prototype. The assertion acts as a trigger condition and the technology captures the design state and the input sequence prior to the trigger.

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