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What is your preferred platform for FPGA Design Flow ?
Windows
55%
Linux
36%
Solaris
1%
Mixed
2%
Other
1%
No preference
4%
Total votes: 4723

Identify

EDA Tool Vendor: 
Synplicity, Inc.

Identify RTL Debugger is the first software tool that allows you to probe and debug your FPGA design directly in the source RTL. You use Identify software to verify your design in hardware as you would in simulation – only much faster and with in-system stimulus.

The Identify tool allows you to navigate your design graphically and mark signals directly in RTL as probes or sample triggers. After synthesis, you view the results in the RTL source code or in waveform. Design iterations are rapidly done using incremental place and route. Identify software is closely integrated with synthesis and routing tools for a seamless development environment.

EDA Tool Category: 
Debugging

Identify Product Benefits

Instrument and debug your FPGA directly from RTL source code
Navigate the design graphically using the hierarchy window. The Identify tool adds icons you use to insert probes, triggers, and breakpoints directly in the RTL source code. All nodes are tagged with a sample or trigger icon. Code branch statements (e.g. CASE or IF statements) are marked as breakpoints. Simply click the icons to setup the debug. Identify software compiles to add the debug logic is added automatically.
Internal design visibility at full speed
After synthesis and routing, you use the Identify solution to store results from the FPGA running at speed. Results are stored on-chip and directly annotated to your source code or viewed in waveform. Probes do not affect performance in any way and require minimal resources.
Incremental iteration
Design changes are made to the device from the Identify environment using incremental compile. You iterate in a fraction of the time it takes route the entire device.
Debug and display results
You gather only the data you need using unique and complex triggering mechanisms. Trigger on an event, a series of events, pulse width, or an absence of an event after a period. Data is annotated directly to the source RTL and you can scroll by clock back and forward in time. Code displays binary and enumerated type values. Data can also be viewed in almost any waveform display.

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