Planet FPGA
- Tired of dealing with rogue software, spyware, and malware?
- Visual Enhancement Engine (VEE) evaluation module from QuickLogic
- Massively parallel processing arrays (MPPAs) for embedded HD video and imaging (Part 1)
- Virtualization Moves Onto Custom Microcontroller
- Samplify announces compression for tomography
Take A Poll
FPGA newsgroup
HDL Analyst®
September 17, 2007 - 10:16am — fc
EDA Tool Vendor:
Synplicity, Inc.EDA Tool Category:
Design EntrySynplicity’s HDL Analyst® tool provides designers with the ability to quickly debug and enhance their Verilog or VHDL code. This is accomplished by providing the designer with graphical representations of their design using a high-level (RTL) technology-independent and technology-specific schematic views. Cross-probing between these schematic
Bookmark/Search this post with:
FPGA Webcasts
Upcoming FPGA Events
- 7 Habits of Successful FPGA Design Workshop - San Jose, CA(Event or Conference)(4 days)
- EDA Tech Forum - Ottawa, ON(Event or Conference)(5 days)
- Multi-FPGA ASIC Prototyping Done Right! - San Jose, CA(Event or Conference)(5 days)
- DVClub Meet-up - Milpitas,CA(Event or Conference)(5 days)
Copyright 2008 @ FPGA Central. All rights reserved.
Forums | IP Catalog | Development Board | Vendor Directory | Products | FPGA Conference | Events | Polls | News | User Blogs | FPGA Jobs USA | FPGA Jobs Portal USA| FPGA Articles | PLD Types
