User login

HDL Analyst®

EDA Tool Vendor:
Synplicity, Inc.
EDA Tool Category:
Design Entry

Synplicity’s HDL Analyst® tool provides designers with the ability to quickly debug and enhance their Verilog or VHDL code. This is accomplished by providing the designer with graphical representations of their design using a high-level (RTL) technology-independent and technology-specific schematic views. Cross-probing between these schematic

Average rating
(2 votes)

Upcoming FPGA Events