Poll

What is your preferred platform for FPGA Design Flow ?:

JTAGTest

jtagtest_sm.png
EDA Tool Vendor: 
SECONS Ltd.

JTAGTest is IEEE 1149.1 JTAG boundary scan debugging, testing and programming solution.

It's invaluable tool for all embedded designers, production houses and service companies. JTAGTest provides a significant aid for PCB debugging, prototyping, testing and repairing. Using an IEEE 1149.1 (JTAG) boundary-scan, device pin signals or internal signals can be monitored in real-time without interfering with the normal device operation and you can change pin state manually. The scan speed can be as high as allowed by your computer and the JTAG connection. Pin state view is provided in listing form or visual chip view:

JTAG Bpundary scan
JTAGTest BGA Chip View

 

Alternatively data can be stored during realtime boundary scan in memory and then viewed as on logical analyzer. All this via 4 JTAG wires:

Waveform view

JTAGTest is multiplatform! Both Microsoft Windows and Linux/Unix are supported!

EDA Tool Category: 
Debugging
EDA Tool Category: 
Design Entry
EDA Tool Category: 
PCB /Board
EDA Tool Category: 
Signal Integrity
EDA Tool Category: 
Verification
EDA Tool Platform: 
Linux
Windows
Windows 2000
Windows 2003
Windows Vista
Windows XP

Key features

  • JTAG IEEE 1149.1 and BSDL compliant
  • Automatic JTAG Scan chain detection
  • Easy to use interface
  • Visualised boundary scan debugging
  • Probing and controlling each pin via JTAG
  • BSDL support
  • Support for thousands of ICs
  • SVF programming (CPLD/FPGA/MCU)
  • SVF automated board testing
  • Hardware supporting more than 20 JTAG pinouts

Requirements

  • PC with Windows 2000/XP/Vista or Linux
  • 256 MB RAM
  • 1GB HDD space (for BSDL files)
  • USB 2.0 port

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