What is your preferred platform for FPGA Design Flow ?:

0-In Formal Verification

EDA Tool Vendor: 
Mentor Graphics

Despite tremendous advances in constraint-random stimulus generation and coverage-based verification, simulation-based verification cannot effectively find all the potential issues within today’s complex chips. This is the main reason that designers complement their simulation-based verification methodology with formal verification.

The 0-In® Formal verification solution offers the highest capacity and performance available along with a set of formal verification engines to help you find your most complex bugs. Together with the extensive CheckerWare® library of monitors and assertions and close integration with your simulation environment. 0-In® Formal represents the leading edge in formal verification, allowing you to not only improve overall verification quality but also find the most critical bugs in your design.

EDA Tool Category: 


* Easy to use. Novices get up to speed quickly with automatic selection of prove-strategies and the user-friendly GUI.
* Full controllability. Formal verification experts can prove the most complex properties and find the most complex bugs.
* Finds the toughest bugs. Powerful formal engines with multi-pass and multi-dimensional optimization.
* Scalable verification. Can be used at the block, sub-system, and system-level through smart integration of formal verification and simulation.
* Extensive proof management. Easy to use analysis and debug GUI leverages familiar schematics and waveforms where appropriate.
* Familiar debugging. Generates traces that can be replayed in simulation whenever bugs are found. Works in conjunction with your existing verification environment and testbenches to find bugs deep in the design.
* Increased functional coverage. Automatically targets coverage points.
* Highest performance and productivity. Particularly when you have hundreds or thousands of assertions in your design.

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