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0-In® Assertion Synthesis
* Automatic and user specified checking of design properties and assumptions
* Easy to specify and maintain assertions throughout a design’s lifecycle
* Rich library of verification IP for RTL structures, standard buses, and major interfaces
* CheckerWare® and CheckerWare Monitor IP
* Uniform handling of multiple, standard assertion language formats
* CheckerWare, PSL, SVA, and OVL
* Automatic insertion of implementation-level functional coverage (structural coverage)
* Aggregation and grading of assertion activity, statistics, and coverage across regression runs
Benefits
* Complete solution for quick adoption of ABV for any design
o Extends capabilities of existing verification environments
o Detects bugs faster and earlier than traditional verification methods
* Increases observability through assertions to accelerate bug detection and debug
* Supports multiple verification engines to maximize assertion value
o Simulators, emulators, and formal verification
* Identifies holes in verification plan and focuses verification resources
o Ensures critical corner cases are tested
o Enables Coverage-Driven Verification
o Improves efficiency of pseudo-random tests with reactive testbenches
* Proven by use at 12 of 15 largest electronics companies in the world
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