Warp CPLD Development Software for PC

Warp(R) is a state-of-the-art HDL compiler for designing with Cypress's CPLDs. Warp utilizes a subset of IEEE 1076/1164 VHDL and IEEE 1364 Verilog as its Hardware Description Languages (HDL) for design entry. Then, it synthesizes and optimizes the entered design, and outputs a JEDEC or Intel(R) hex file for the desired PLD or CPLD (see Figure 1). Furthermore, Warp accepts VHDL or Verilog produced by the Active-HDL FSM graphical Finite State Machine editor. For simulation, Warp provides a timing simulator, as well as VHDL and Verilog timing models for use with third party simulators.

Feature
VHDL (IEEE 1076 and 1164) and Verilog (IEEE 1364) high-level language compilers with the following features
Designs are portable across multiple devices
and/or EDA environments
Facilitates the use of industry-standard simulation and synthesis tools for board and system-level design
Support for functions and libraries facilitating modular design methodology
IEEE Standard 1076 and 1164 VHDL synthesis supports
Enumerated types
Operator overloading
Generate statements
Integers
IEEE Standard 1364 Verilog synthesis supports
Reduction and conditional operators
Blocking and non-blocking procedural assignments
While loops
Integers
Several design entry methods support high-level and low-level design descriptions
Behavioral VHDL and Verilog (IF...THEN...ELSE; CASE...)
Boolean
Aldec Active-HDL(TM) FSM graphical Finite State Machine editor
Structural Verilog and VHDL
Designs can include multiple entry methods (but only one HDL language) in a single design
UltraGen(TM) Synthesis and Fitting Technology
Infers "modules" such as adders, comparators, etc., from behavioral descriptions and replaces them with circuits pre-optimized for the target device
User selectable speed and/or area optimization on a block-by-block basis
Perfect communication between synthesis and fitting
Automatic selection of optimal flip-flop type
(D type/T type)
Automatic pin assignment
Ability to specify timing constraints for all of the Delta39K and PSI devices
Supports all Cypress Programmable Logic Devices
PSI(TM) (Programmable Serial Interface)
Delta39K(TM) Complex Programmable Logic Devices (CPLDs)
Ultra37000(TM) CPLDs
FLASH370i(TM) CPLDs
MAX340(TM) CPLDs
Industry standard PLDs (16V8, 20V8, 22V10)
VHDL and Verilog timing model output for use with third-party simulators
Timing simulation provided by Active-HDL(TM) Sim Release 3.3 from Aldec
Graphical waveform simulator
Entry and modification of on-screen waveforms
Ability to probe internal nodes
Display of inputs, outputs, and high impedance (Z) signals in different colors
Automatic clock and pulse creation
Support for buses
Architecture Explorer and Dynamic Timing Analysis for PSI and Delta39K devices
Graphical representation of exactly how your design will be implemented on your specific target device
Zoom from the device level down to the macrocell level
Determine the timing for any path and view that path on a graphical representation of the chip
Static Timing Report for all devices