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BoardPlanner Co-Design
March 10, 2008 - 11:35am — mwilson
EDA Tool Vendor:
Cadplex Software LLCEDA Tool Platform:
Other Windows
EDA Tool Category:
PCB /BoardBoardPlanner Co-Design allows the User to optimize the design of both the FPGA and the PCB simultaneously. It can optimize the FPGA I/O pins based on where the parts are placed on the board. This reduces crossing counts and wire lengths. It allows the board routing to be optimized before the FPGA design is complete. Works in Cadence, Mentor or mixed design tool environments.
Major features:
- Automatically optimizes the FPGA I/O pins for best routability on the board.
- It then back annotates the pin swaps to the FPGA Design tool thru UCF file.
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