Poll
HES
HESâ„¢ is a versatile emulation and acceleration solution for large complex ASIC & SOC designs which require millions of simulation cycles. The strength of the tool is in automatic design compilation, standard testing interface, integration with industry leading hardware/software debugging tools and the power to transform your existing ASIC prototyping into dynamic emulation.
Top Features
- SOC (both ASIC and FPGA)
- Functional simulation acceleration
- Transaction Level interface (SCE-MI, SystemC C/C++)
- Internal Debugging
- The DINI Group and Synplicity HAPS platform support
Hardware Assisted Verification
HESâ„¢ provides no-hassle ASIC and FPGA design compilation to the hardware with automatic design partitioning, clock domain conversion, memory mapping and many other techniques. HESâ„¢ can target a commercial of the shelf
prototyping platform such as DINI and HAPS for hardware emulation and acceleration.
Emulation
HES™ provides functional verification of entire design in multi FPGA platform. The design is exercised using real data flowing through transaction level interface such as industry standard SCE-MI interface or C/SystemC API. Built-in debugging tools allow quick localization and capturing of bugs quickly. Additionally, HES™ supports interface to Novas® Siloti™ and Verdi™ for RTL annotated debugging.
Acceleration
Another application of HESâ„¢ is acceleration of functional
simulation. The design is offloaded to the hardware and
exercised by the HDL test bench running in logic simulator.
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