ALINTÃƒÂ¢Ã¢â‚¬Å¾Ã‚Â¢ is a highly optimized design rule checking system currently supporting VerilogÃƒâ€šÃ‚Â® HDL language. The product includes a complete set of STARC Design Style Guide rules to use in your next ASIC design. STARC is a consortium of 11 Japanese ASIC foundries that has established a set of design rule guidelines for corporations to follow based on a set of best-design practices.
- Verilog Code checks, design elaboration and synthesis emulation
- Clock Domain Crossing (CDC)
- User Defined Design Rules
- Fast analysis of complex ASIC/FPGA-SOC designs
- Cross-probing of Error messages to source code
- Support for STARC Design Rules
Open ALINT configurator and select the set of rules most suitable for your design. If necessary, adjust parameters of individual rules to fine-tune design checking to meet requirements. Adjust options to execute only code checks for quick evaluation of your design, or enable design elaboration for thorough evaluation.
Cross-Probing and Error Detection
ALINT includes a clear and informative set of messages that are generated during checking and a direct cross-link with the Verilog source code to ensure high efficiency of work and significantly shorten design schedule.
Review messages created by ALINT. The error messages will provide you with a good understanding of what is taking place within your design. Utilize built-in cross probing and error detection to take you directly to the source code in which the error was detected.
Advance Violation Database, AVDB stores violation reports which can be filtered using combinations of criteria such as rule, severity, instance, source file and more. AVDB manages different project revisions and enables easy change tracking.