Aldec DO-254 Tool Set

HDL Simulation tool suite
Aldec DO-254-CTS provides RTL simulation (Source Level), post-synthesis simulation (Gate Level) and post place-and-route simulation (Timing). The HDL Simulation tool suite uses a set of HDL testbenches to verify the design functionality and code coverage. The results are stored in signal database files such as waveforms, text or VCD files. Code Coverage and Code Linting are included in the HDL Simulator tool suite. Code Coverage validates testbenches are providing adequate design testing. To further enhance verification productivity, the HDL simulator tool suite comes with Profiler, Documentation features and Waveform Comparison.

In-Hardware Simulation
Aldec DO-254-CTS features Hardware Embedded Simulation (HES) technology, with the design implemented in the target FPGA on a customized daughter board. In-Hardware simulation is driven by the same testbench or set of vectors as used for RTL simulation. The results of the hardware simulation are stored in the waveform, text or VCD file and can be compared to those obtained during the event driven RTL simulation. Designers are able to use the same testbench and set of test vectors or transactions for validation of RTL code, both in the software simulator and for the In-Hardware Simulation.

In-Hardware Simulation with a Testbench
In this mode, the design in the target FPGA is driven (on an event basis) by the same HDL Testbench as used during RTL simulation. Aldec/DO-254 CTS provides a co-simulation channel that drives the inputs and reads the outputs of the design. Results of in-hardware simulation are available on-the- fly as during regular simulation for analysis and comparison. This mode is ideal for a functional check and qualification of the HDL verification tools.
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In-Hardware Simulation with Test Vectors
In this mode, the design in the target FPGA is driven by test vectors captured during RTL simulation and stored in waveform format. The values obtained from the outputs of the design running at speed are read back and recorded in the output waveform file for further analysis. This mode is ideal for at-speed testing and qualification of HDL verification tools.

At-Speed Verification –Compliance Assurance
Aldec DO-254 CTS provides assurance that the hardware item implementation meets the compliance requirements. In the verification flow, testing requirements are checked first in the HDL simulator and later in the target hardware. Aldec offers the convenience of checking all testing requirements in the HDL simulator, where an engineer can drive or probe any signal. Typically, when a design is tested in hardware it lacks flexibility and traceability. Since it is not always possible or easy to check all test scenarios, typically only major design functions are verified in the product hardware. Additional analysis is then required to prove the coverage of the lower level of requirements. Aldec’s DO-254 compliance tool-set bridges this gap in the verification process. By using the test vectors directly mapped from the HDL testbench, customers receive the flexibility of the simulation test vectors in the hardware. Test vectors with 100% test coverage can be reused in hardware testing and all FPGA outputs are captured in waveform format for easy viewing, analysis and traceability with the design test requirements and RTL simulation results.