Active-HDL

Intuitive Design Entry Tools
You can learn new languages as you design, with the built-in language assistant for VHDL, Verilog®, SystemVerilog and SystemC that provides pre-defined templates, embedded language reference manuals and type-ahead command completion. Draw powerful finite state machine diagrams and let the tool generate your synthesizable RTL code. Quickly connect all design modules at the top-level, and output structural HDL using the built-in block diagram editor. Code-to-graphics tools allow you to easily visualize designs imported from VHDL, Verilog or EDIF.

High Performance, Mixed Language Simulation
Active-HDL includes a high performance, common-kernel, mixed language simulator supporting Verilog, System Verilog, VHDL, VITAL, SDF, EDIF, and SystemC on Window-based 32/64 bit platforms. Drive your system-level simulation model using complex testbenches or create quick and flexible stimulators to rapidly test design modules. Co-simulate MATLAB functional DSP blocks with HDL models in a high-level mathematical modeling environment.

Debugging Made Easy
Active-HDL includes highly intuitive, graphical debugging tools including a high performance waveform viewer/editor, graphical dataflow for tracing signal drivers/readers across multiple levels of design hierarchy and quickly traces unknown values to their origin.

Code Coverage Analysis and Linting
A powerful HDL code coverage analyzer helps achieve 100% test coverage of RTL statements, lines, signals and logical expressions in the design. An embedded lint tool checks for reliable, predictable and portable HDL code.
Team Based Design Management
Increasing design size and complexity requires a team based approach for many projects. Active-HDL links to most source control software, has a built-in server farm manager to automate regression testing, and provides multi-design workspaces to enable collaboration. Produce finish-quality, system-level documentation in HTML and vector-based PDF with hierarchical hot-links