Planet FPGA
- Tired of dealing with rogue software, spyware, and malware?
- Visual Enhancement Engine (VEE) evaluation module from QuickLogic
- Massively parallel processing arrays (MPPAs) for embedded HD video and imaging (Part 1)
- Virtualization Moves Onto Custom Microcontroller
- Samplify announces compression for tomography
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CoreConsole
The CoreConsole IP Deployment Platform (IDP) and block stitcher has been developed to enable designers to quickly assemble system-level designs and to simplify the construction of a processor subsystem and assembly of IP blocks within a design. The CoreConsole IDP is a front-end design entry tool that enables IP blocks to be stitched together into synthesizable and simulatable RTL that can be exported into Actel's world-class Libero IDE FPGA development tool suite. The CoreConsole IDP enables users to focus on the system rather than individual components, allowing them to evaluate system-level performance earlier in the design process and reduce overall development time.
Key Features
Enables rapid assembly of system-level designs
IP deployment platform with secure IP vault
Supports IP block stitching and configuration
Intuitive, easy to use graphical user interface (GUI)
Users can add their own IP cores
Automatic system testbench generation
Includes configurable processor subsystem blocks
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- DVClub Meet-up - Milpitas,CA(Event or Conference)(5 days)
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