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SystemVerilog for Verification: A Guide to Learning the Testbench Language Features
Published on:
2008Publisher:
Springer-Verlag; 2Rev Ed edition Buy the Book Now (from Amazon):
ISBN-10:
0387765298ISBN-13:
978-0387765297ASIN:
0387765298Book Category:
VerificationSystemVerilog for Verification teaches the reader how to use the power of the new SystemVerilog testbench constructs plus methodology without requiring in-depth knowledge of Object Oriented Programming or Constrained Random Testing.
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