World's Largest FPGA/CPLD Portal
System Test and Validation Engineer opening at Silicon Image in Sunnyvale, CA
Local Candidates Preferred. 2+ Yrs. of experience in designing tools for Automatic Chip Validation.
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Position Requirements
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Experience : minimum of 2 years
Must be proficient in logic design & debug in Verilog for FPGA. o Able to do schematic capture and board design. o Knowledge of RS-232, USB, I2C, Digital video standards, HDM/HDCP and DVI protocols. o Knowledge of Assembly and C/C++ programming languages o Hands on knowledge of logic analyzers, oscilloscopes, JTAG, in circuit emulators and their use for hardware and firmware debugging o Prior experience in using Labview is a plus. o Good written and oral communication skills. Ability to clearly document. |
If you are interested in this opening, please send me a soft copy of your resume at [email protected].
Thanks,
Rani
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About Author
Last Name
Bagai
First Name
Rani
Employer
Silicon Image
About Myself
Recruiter at Silicon Image in Sunnyvale, CA
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FPGA Central is a website bringing the FPGA (Field Programable Gate Array), CPLD , PLD, VLSI community together at one central location. Some Keywords: FGPA, FPGA, EDA Tools, FPGA Design, Central, Programmable logic, LUT, VLSI, SoC, Journal
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