System Test and Validation Engineer opening at Silicon Image in Sunnyvale, CA

March 9, 2010 - 12:37pm — ranibagai

Local Candidates Preferred. 2+ Yrs. of experience in designing tools for Automatic Chip Validation.

Position Requirements

Experience : minimum of 2 years
Must be proficient in logic design & debug in Verilog for FPGA.
o Able to do schematic capture and board design.
o Knowledge of RS-232, USB, I2C, Digital video standards, HDM/HDCP and DVI protocols.
o Knowledge of Assembly and C/C++ programming languages
o Hands on knowledge of logic analyzers, oscilloscopes, JTAG, in circuit emulators and their use for hardware and firmware debugging
o Prior experience in using Labview is a plus.
o Good written and oral communication skills. Ability to clearly document.

If you are interested in this opening, please send me a soft copy of your resume at siliconimage2010@yahoo.com.

Thanks,

Rani

ranibagai's blog
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System Test and Validation Engineer opening at Silicon Image in Sunnyvale, CA

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