Step-by-Step Description for MATLAB+ISE Co-Simulation using System Generator for Spartan/Virtex FPGAs

Planet FPGA

INTRODUCTION

In this Post,we will discuss step by step explanation of MATLAB+ISE Co-Simulation.

We use these methods for Prototype Development. For example here I am explaining how to write a Generalized Program for Line Equation in FPGA.

The program has to be written in such a way that if the inputs are changed, according to the logic written, output should be calculated. For this we can use MATLAB+ISE Co-Simulation and Hardware Co-Simulation.In next post Hardware Co-Simulation will be discussed.

The software I have in my computer are;

• Matlab R2008a
• Xilinx ISE 11.4
• System Generator 11

Program- Line Equation Program for Demo purpose

HDL used-Verilog

STEPS:-

Start By,

open Xilinx ISE

Go to File > New Project

after Clicking to New Project , the following window comes

Select Target Folder where you want to save your Project.

I have selected path D:\FPGA KAAM\st_line_demo which is my path before creating project.

Type the Create Name,I have given st_line name

By default st_line folder will get created in the destination that one has selected.

obesrve in screenshot that D:\FPGA KAAM\st_line_demo\st_line

Proceed by Next>

Device Properties window occurs,

Select the device you are using ,select the Preferred Language>I have used Verilog,

Click on New Source,

The following window comes,

Here I am wiritng program in Verilg HDL,so I have selected Verilog Module and give the file name,I have given stln,

Click on Next>

We will see Define Module Window,

here,we can define the Inputs and Outputs,specify their structure as if weather it is a single bit or Bus of specific bit length.

I leave it blank every-time because I write them in direct program itself,both are valid.

Click Next>

then Click Next> until you get the following window,

Click on Verilog Module as shown below so you get your Verilog File which Looks like,

The structure of the program will be as follows,

I have used here Verilog Program for Stright Line which is a follows,

After writing the whole code,double click on Synthesis,
Once synthesis is complete Open System Generator,

MATLAB & SIMULINK will get open,

From Simulink Library Browser Window click on >File > New > Model--- OR---- directly click on

Now one Untitled model window will get open,

go to File > Save as >

Important NOTE Browse & go to the folder in which we have saved our Project Save the Model file,

in this case the folder is "D:\FPGA KAAM\st_line_demo\st_line " in our case .

Save Model file in the same Folder as explained.

I have saved my Model file in D:\FPGA KAAM\st_line_demo\st_line with name str_line

Now go to Simulink Library Browser as shown below,

Goto Xilinx Blockset >Basic Elements > (on right hand side) Select System Generator and Drag & Drop,System Generator---OR---right click on System Generator> Add to str_line i.e. filename

Exactly same way as done for System Generator ,add Black Box(for more info. have a look at Block Description on bottom of the same window) and Drag & Drop, Black Box ---OR---right click on Black Box> Add to str_line i.e. filename

After this step,the following window will occur,

This window automatically pops-up.Here we have to give the Veilog/VHDL file path,for my case I have given the name stln.v

Select .v file & Click on Open,

Black Box will take the Inputs & Outputs as we have defined in our program for this program recalling,

module stln(clk,ce,y,c,m);
input clk,ce;
input [7:0] m,c;
output reg [31:0] y;
integer x,z;

Here we have used,

m,c as inputs,

y as output,

x,z as Intermediate Variables,

so Black Box has Taken only inputs & Outputs,

To give input & take output we have to use Input Gateways & Output Gateways respectively.

Insert both Gateway in & Gateway out as done with Black Box to import them to our Model File.Connect as shown below,

Important we have to Configure the Gateway in Block,as to match the Input we are giving to Black Box with the Bit Structure(No. of Bits,Signed,Unsigned etc.) we have specified in our Program.

say for example 2 can be represented in 8 bits & 16 bit differently.so if we want to input 2 into the black box input m,we have defined input [7:0] m,c; as 8 bits (0 to 7),so 2 should go in 8 bit format.

for the same we will Double Click on Gateway in>

Here we will specify as 8 bit Unsigned.Repeat the procedure for the no. of Gateway ins you have.

No need to configure Gateway out.

From Simulink Library Browse,

Pick Simulink > Sources > Constant,

Pick Simulink > Sinks > Scope & connect as shown,

Important it is necessary to configure Black Box Simulation Mode from Inactive to> ISE Simulator Mode,

for this Double Click on Black Box,thus property window as shown below will get open,

By default Simulation Mode is Inactive.Make it as ISE Simulator & then click on OK,

Now the model is ready to run,

Click on Start Simulation Button,

Once Simulation Runs, Double Click on Scope,

as can be seen it shows discrete steps,by default Simulation Stop time is 10.0,if we change it to 100 as shown below,

then click on Start Simulation, the model so the output generated output will be,

Change in output can be observed by changing the values of Constants (the present values are 5 & 6 for m & c respectively).

Likewise we can use MATLAB+ISE Co-simulations for no. of programs that you want to make for FPGA & test it for different inputs.

Hope we can share more ideas on the same :)

Vihang Naik,
M.Tech-II-Instrumentation & Control,
Embedded Design Center,
Dept. of Instrumentation & Control,
College of Engineering Pune.