JTAGTest: JTAG IEEE 1149.1 Debugging and Testing Solution

SECONS has launched JTAGTest, IEEE 1149.1 debugging and testing tool. Main features include:

  • JTAG IEEE 1149.1 and BSDL compliant
  • Automatic JTAG Scan chain detection
  • Easy to use interface
  • Visualised boundary scan debugging
  • Probing and controlling each pin via JTAG
  • BSDL support
  • Support for thousands of ICs
  • SVF programming (CPLD/FPGA/MCU)
  • SVF automated board testing
  • Hardware supporting more than 20 JTAG pinouts

JTAGTest is invaluable tool for all embedded designers, production houses and service companies. JTAGTest provides a significant aid for PCB debugging, prototyping, testing and repairing. Using an IEEE 1149.1 (JTAG) boundary-scan, device pin signals or internal signals can be monitored in real-time without interfering with the normal device operation and you can change pin state manually. The scan speed can be as high as allowed by your computer and the JTAG connection.

It is possible to use this program during FPGA development, for example to verify design functionality or force pin states in order to test other circuits.

In addition to boundary scan testing, the tool provides also SVF programming and can be used to load bitstream into your FPGA or configure CPLD.

 

About Author

Last Name
Hinner

First Name
Martin

Employer
SECONS Ltd.

Facebook  Twitter  Linkedin  YouTube      RSS

 

Check out FPGA related videos

Find Us On Facebook