Platinum Sponsor
Featured Article
ESC - Embedded System Conference - Silicon Valley, CA
Apr 26 2010 8:00 amApr 29 2010 6:00 pmESC is the fastest-growing embedded event in the world, with events happening year-round in locations as Silicon Valley, Boston, India, the UK and France.
FPGA Poll & Survey
Planet FPGA - All FPGA blogs at one place
Tutorial
TopJTAG Probe: Low-cost Boundary-Scan (IEEE 1149.1 JTAG) Circuit Debugging Software.
TopJTAG announced a release of TopJTAG Probe –- a low-cost boundary-scan (IEEE 1149.1 JTAG) based software for circuit visualization and debugging. The software allows to observe and to control pin states of any JTAG-compliant device in a JTAG chain. Pin states are displayed and updated in real-time on a graphical package view. There is a possibility to record waveforms of pin signals.
BYPASS, SAMPLE, EXTEST and INTEST boundary-scan instructions supported. So in addition to monitoring pin states without interfering to a working device operation (in SAMPLE mode), the software can be used to drive pins to test circuit interconnects (in EXTEST mode) and to test chip’s internal logic (in INTEST mode). As CPLDs are not supported by tools like Xilinx ChipScope and Altera SignalTap, boundary-scan is the only method to debug CPLD firmware.
Some of the benefits of using TopJTAG Probe:
- Monitor and control pins without touching a board.
- Easily access pin signals of BGAs and fine-pitch devices.
- Interactively set up pin values to check board-level interconnects for shorts and opens.
- Test on-chip internal logic, e.g. debug CPLD firmware.
- Debug prototype designs and detect PCB defects.
TopJTAG Probe can work with many popular JTAG cables.
- ksa's blog
- Login or register to post comments
Upcoming FPGA Events
- Accelerating Custom IC Layout with IC Station - San Jose, CA(Event or Conferences)(3 days)
- RocketLaunch webinar(Webcast)(5 days)
- How Physical Implementation realizes Power Intent Web Seminar(Webcast)(10 days)
- U2U - User 2 User conference - Santa Clara, CA(Event or Conferences)(17 days)
- RocketLaunch webinar(Webcast)(24 days)
Copyright 2008 @ FPGA Central. All rights reserved.
FPGA Central is a website bringing the FPGA (Field Programable Gate Array), CPLD , PLD, VLSI community together at one central location.
Some Keywords: FGPA, FPGA, EDA Tools, FPGA Design, Centeral, Programmable logic, LUT, VLSI, SoC, Journal
Terms Of Use | Privacy Policy | About Us | Add to Site | Advertise with Us | Blog | Feedback | Powered By Lamingo Creator of eLagaan
  