Unique Solutions for a Demanding Market Space

Consumer Handheld Challenges

Traditionally, FPGAs have avoided the consumer handheld market during to its stringent requirements for low power, low cost, and small space. As consumer electronics become more sophisticated, new technology breakthroughs in manufacturing, packaging, and display solutions emerge. Market dynamics remain affected by the same factors: price, power and space. These factors pose serious challenges to designers trying to meet market requirements and produce leading edge products, while meeting tight schedules due to very short production cycles. These challenges can present serious limitations to handset development, especially with the rising competition in the consumer space and the need for differentiation in a very competitive market. While custom ASICs fulfill some of the designers needs, programmable logic provides the reprogrammable flexibility and time-to-market to meet these design challenges. Existing programmable logic companies have attempted to tackle these challenges, but their solutions have fallen short of being complete and optimum. SiliconBlue is the only company to build from the ground-up a new generation of SRAM based FPGAs that meet the needs of this expanding industry. Below, we present these challenges and the unique solutions that SiliconBlue offers customers, to enhance handheld designs from concept to production.The key challenges for handheld designs are summarized in the table below, with respective SiliconBlue solutions:

Table 1: Handheld Challenges and Solutions

Challenges Solutions
Meet Power Budget Ground-Up Ultra-Low Power Circuit Design
Maintain Short Production Schedule Complete Design Environment
Multiple Functionalities in Small Space High-Density Gate Count with 65 nm LP Process
Keep Low Cost BOM One chip Solution with NVCM on a Standard High-volume TSMC Process


SiliconBlue Answers to Market Challenges

SiliconBlue Technologies offers the programmable logic industry a new FPGA family specifically designed for the expanding consumer handheld market, dominated by low-power consumption requirements.

To illustrate how SiliconBlue iCE FPGAs benefit the handheld designer, the diagram below summarizes all key advantages in a handheld platform. The inner ring summarizes the unique technology advantages backed up by application, quality and reliability. Each key technology relates to multiple advantages for the designer on the handheld platform. For instance, the market is in need for a single chip solution to reduce space and provide a secure bitstream. The patented NVCM (Non Volatile Configuration Memory) technology on standard CMOS process enables a single chip solution while completely eliminating the risk of bit snooping or alterations.

Figure 1: Market requirements, Key offerings, and handheld benefits

When all SiliconBlue offerings are considered together, the value proposition becomes unique
in the industry.


Table 2: SiliconBlue iCE Device Family

  iCE65L02 iCE65L04 iCE65L08 iCE65L16
Logic Cells 1,792 3,520 7,680 16,896
Programmable I/O 128 176 222 384
RAM4K blocks 16 20 32 96
Standby current (typical) 25 µA 50 µA 100 µA 250 µA

 

 

 

 

 

In the remaining portion of this article, we present the extent of competitiveness of SiliconBlue in the market by using three standard metrics: Price, Power and Space. Finally, we present the iCE development platform that designers can use to quickly and reliably prototype their handheld designs.

iCE reduces price, power, and space

With the proliferation of handhelds in consumer electronics, competitiveness has risen and price has dropped drastically. Designers are also trying to include new innovative features into each succeeding product family. SiliconBlue today offers handheld designers exactly that capability, through its advanced TSMC 65nm LP process technology! SiliconBlue has a patented technology that delivers non-volatile configuration memory using a standard, high-volume, low-power, low-cost 65 nm CMOS production process, which eliminates the need for any external components. Furthermore, using the standard 65 nm LP production process eliminates any special fab handling and further reduces manufacturing costs. The 65 nm process enables SiliconBlue to create high-density parts at lower cost, reducing the cost per gate by an order of magnitude or more compared to competing programmable logic families. Figure 2 shows the relative cost per logic cell for various popular, consumer-market FPGAs. For the price of an 8K LUT device from SiliconBlue, designers can see the meager equivalent in other PLDs and FPGAs.

Figure 2: Number of logic cells of iCE versus Competitive PLDs for same dollar amount

When it comes to the power dilemma, SiliconBlue offers the lowest power in the industry. iCE FPGAs are designed from the ground up using power-conserving design techniques. Power budgets were engineered for each portion of the chip in order to meet the total power consumption budget. Using specially-selected library components from top-tier partners enabled SiliconBlue architects to meet or exceed the tight power budgets demanded by handheld applications. Furthermore, while other PLD or PFGA vendors specify their products power consumption either a zero MHz or in special, non-functioning “standby” mode, iCE FPGAs deliver their lowest power while actually operating at 32 kHz, without a need for deep-sleep or clock-stop modes. For example Power consumption on an iCE65L04 device filled with 192 16-bit counters yields ultra-low 25 µW at 32 KHz! In a typical cell phone application, this means that basic system functions or heart-beat applications use minimal power. The table below details the power consumption numbers in mW of iCE device at 32 kHz and active frequency of 32 MHz, and compares it to other PLDs and FPGAs.

Table 3: iCE Power Consumption in Stand-by and Active more

Portable devices constantly drive toward smaller PCB sizes and smaller component footprints. Oftentimes, this push toward higher integration comes at the expense of extra features. Today, with TSMC 65 nm LP process, SiliconBlue offers ultra-small package sizes and the option to use bare die and bumped bare die for chip-on-board or stacking with other components.Other programmable logic families utilize embedded flash memory for configuration, which lags two process nodes behind SRAM technology, so they are unable to produce leading edge die size with the associated smallest package. The issue is further complicated for SRAM-based FPGAs where the configuration memory is typically a separate flash memory component in the system. The complete family of SiliconBlue iCE65 FPGAs is available in small package footprints that occupy minimum PCB space, due to 65 nm process technology, the patented nonvolatile configuration memory and advanced packaging solutions from partners TSMC and ASE.Typically, the smaller the package size, the less user I/Os are available. Designers can choose from a family of products and accordingly select the appropriate footprint for the application. iCE high logic density and packaging technology allow handset designers to consolidate more functionality on the same silicon occupying the same area. Figure 3 shows the Wafer Level Chip Scale footprint with 63 balls providing up to 45 user-I/Os. An example handset design shows the limited space that a PCB designer can afford for programmable logic. SiliconBlue iCE65 devices and their aggressive packaging options allow designers to uniquely integrate large amounts of programmable logic in the limited space available.

Figure 3: iCE small footprints are ideal for minimum space in a handset design

LCD Display Controller Demo

This application demonstrates the implementation of a graphics LCD controller, a touch screen controller and a NAND Flash interface on an iCE FPGA. The following are the various blocks implemented using our iCE L04 device with 4K LCs:
Block Address Decoder: It monitors the outputs from the touch screen controller and provides the address of the location in the address RAM where the image is stored.

NAND Read Controller: It retrieves the image data from the NAND flash in a phased manner. At any time a single page of data is fetched from the flash memory, containing four lines of display data.

Display RAM: the display RAM is an extremely small buffer realized using four 256x16 dual port RAM blocks of the iCE device. It totals 2 KB in size and is capable of storing four display lines worth of pixel data at a time.

Graphic LCD Controller: Generates the various QVGA signals required for driving the LCD display.

Power Sequence/Debounce Logic: Constantly monitoring the status of the on_off_sw on the iCE development kit. The block diagram in figure 4 shows all the various blocks implemented for this application.

Figure 4: Display Controller IP

Table 3 contains utilization numbers for the iCE device; including logic utilization, RAM blocks usage, and operating frequency. Internal current consumption is on average equal to 1.8 mA!

Table 4: LCD Display Controller Utilization and Power Consumption

iCE Device Logic Utilization RAM Blocks Frequency (MHz) Power Consumption (mA)
iCE65L04-UCB284 1,475 5 14.318 1.8

Figure 5 shows the prototype of the LCD Display Controller using the iCEman evaluation board and a plug-in module with a Topology LCD.

Figure 5: LCD Display Controller

Versatile Handheld Development PlatformHandset applications have a short production cycle so handset designers have little time to turnaround a working product. The market is extremely competitive and vendors target specific market windows or seasons. Consequently, the SiliconBlue development platform allows designers to quickly turnaround a functioning design with minimal or no overhead. The system consists of the following elements.

iCEman65 Evaluation Board: A complete hardware and application development platform that provides test points for power measurements. The evaluation board can be populated with various device sizes and package options and has multiple connectors for external connectivity. Also, memory interface standards and LVDS signaling is supported on the left bank. There is one 32 kHz crystal on the bottom of the board and a socket for a 32 MHz oscillator. The iCE device is programmed either from an SPI interface or through the JTAG interface. The iCEman board also has 8Mbit SPI serial flash to hold one or more configuration bitstreams for an iCE device, useful during development. The iCE-F device includes nonvolatile configuration memory although it too can be programmed from SPI serial Flash. The iCEman65 evaluation board also supports the iCE65 cold boot and warm boot functionalities where more than one configuration image can be selectively loaded into the device.

iCEcube Software: Partnering with Magma, SiliconBlue development software is easy to use and provides optimum placement and routing for various types of patterns. VHDL or Verilog logic synthesis and placement were created by Magma while routing and bitmap generation was integrated by SiliconBlue.

Intellectual Property: The iCE65 IP portfolio ranges from basic IP functionalities such as voltage level translation and GPIO expanders to more complex functionalities such as an LCD display controller and Image Rendering Engine. Figure 4 shows the three main segments

Figure 6: iCE Development Platform is versatile and easy to use

Summary

The battery operated market space in general and the handheld space in specific, have been long awaiting the ultimate solution that stretches battery life, reduces system cost, and offers modern FPGA features in a compact package. The SiliconBlue iCE65 family is specifically designed as the ultimate programmable logic solution for the handset market. While high density FPGA fail at keeping low power consumption low when increasing logic densities, others fail to meet logic density and cost target when aiming for a low power programmable solution (Low Power CPLDs).

About the Author

Ibrahim Khozam is System Applications Engineer at SiliconBlue. Prior to joining SiliconBlue, Ibrahim was an FAE (Field Applications Engineer) at Marvell Semiconductor focusing on their applications processors.

In addition, Ibrahim worked in system design at Intel Corporation within the company's Xscale processor product line. Ibrahim holds both undergraduate and masters degrees in computer engineering from San Jose State University, where he graduated with honors.

You can contact the author by login to this portal and visiting his profile here.  

About Author

Last Name
Khozam

First Name
Ibrahim

Employer
SiliconBlue Technologies

About Myself

System Applications Engineer at SiliconBlue. Prior to joining SiliconBlue, Ibrahim was an FAE (Field Applications Engineer) at Marvell Semiconductor focusing on their applications processors.
In addition, Ibrahim worked in system design at Intel Corporation within the company's Xscale processor product line. Ibrahim holds both undergraduate and masters degrees in computer engineering from San Jose State University, where he graduated with honors.

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