Dynamic Partial Reconfigurability of FPGA's

Now a days FPGA’s have become the number one choice for any Hardware Developer when it comes to ASIC design or Future proof design. Over the last 12 years FPGA’s have grown to mind boggling proportions in the number of gates per FPGA and the variety of ip-blocks avialble . They have in fact overlapped some the functionality of an ASIC/ASSP and in some areas surpassed their performance.

One the most outstanding features of FPGA’s that have given them the edge over ASIC/ASSP is their full cum partial dynamic reconfigurability. I have drawn a concept of how to use an Altera Cyclone-ll FPGA to implement a multiple of DSP Filter blocks as they are required or as the monitoring engine sees fit. In this scheme its a 32-bit Nios-ll processor as a monitoring engine, which is provided by Altera in their FPGA IDE Quartus-ll. In this layout Nios-ll acts a supervisor/controller, while the rest of the silicon is left for DSP Blocks to be implemented. Whenever there is need to change the configuration the Nios-ll instructs the Configuration Controller to address the one the three DSP Filter configuration from the Configuration EEPROM. Only the area designated for DSP Filter block implementation is configured. Since Nios-ll is the master controller in this hardware layout , there is user interface which includes a keypad and a LCD display. The user can analyse the results of filter on the LCD and if required choose a different configuration to be used . There can be numerous possibilities in which this hardware can be used by only using one FPGA with its ability to partially reconfigure itself. The RAM connected to the FPGA is to store the processed data and to analyse it. Cyclone-ll FPGA’s i/o allow very fast data transfers compatible to DDR-ll and also high speed ZBT RAM.
If the application required to process the data by all three DSP Filter types, the Nios-ll can be programmed to swap all of the three Filter types one by one . As Cyclone-ll can clock its internal RAM blocks (M4K Blocks) at 250Mhz some of initial data can be buffered using these bocks and after a new configuration is downloaded , it can then be processed through a second filter in real-time.  
FPGA are best suited for DSP application, since their dsp ip blocks process data in parallel ( using their EMB Embedded Multiplier Blocks ) and compute complex calculations in less clock cycles then their ASIC/ASSP counterparts. These EMB can be used in two formats either signed or unsigned and data width range from 9-bit to 18-bit. The internal clock speed for Cyclone-ll FPGA’s range from 100Mhz to 400Mhz, depending on their speed grade. The PLL blocks available on Cyclone FPGA’s can also be dynamically configured , thus they can be adapted to generate different clocks for different configurations.
Thus FPGA’s continue to be a Hardware Design Engineer’s white board. These devices are becoming more flexible ,offer a variety of high speed serial interfaces, high speed general purpose i/o’s , memory blocks , dsp cores , clock management, embedded microprocessor ip cores , testing/debugging using JTAG and full/partial reconfigurability.
By: A.A.Ghouri
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