BEGIN:VCALENDAR
VERSION:2.0
METHOD:PUBLISH
X-WR-CALNAME:FPGA Central | October 11\, 2008 - November 10\, 2008 | Filter\: 
PRODID:-//strange bird labs//Drupal iCal API//EN
BEGIN:VEVENT
DTSTAMP;VALUE=DATE:20081011T143205Z
DTSTART;VALUE=DATE-TIME:20081013T170000Z
DTEND;VALUE=DATE-TIME:20081016T020000Z
UID:http://www.fpgacentral.com/fpga-event/2008/oct/vlsi-soc-2008-greece/rhodes-island-greece
URL;VALUE=URI:http://www.fpgacentral.com/fpga-event/2008/oct/vlsi-soc-2008-greece/rhodes-island-greece
SUMMARY:VLSI-SoC 2008 - Greece
DESCRIPTION:<p>VLSI-SoC 2008 is the 16th in a series of international conferences\,<br />
 sponsored by IFIP TC 10 Working Group 10.5 (VLSI) and IEEE CEDA that</p>
 
END:VEVENT
BEGIN:VEVENT
DTSTAMP;VALUE=DATE:20081011T143205Z
DTSTART;VALUE=DATE-TIME:20081016T140000Z
DTEND;VALUE=DATE-TIME:20081016T150000Z
UID:http://www.fpgacentral.com/fpga-event/2008/oct/europe-webinar-aldec%C2%AE-and-zuken%C2%AE-pin-syn/online-thursday-october-16-2008-300-pm-
URL;VALUE=URI:http://www.fpgacentral.com/fpga-event/2008/oct/europe-webinar-aldec%C2%AE-and-zuken%C2%AE-pin-syn/online-thursday-october-16-2008-300-pm-
SUMMARY:Europe Webinar Aldec® and Zuken®\: Pin Synchronization for Smooth Integration of PCB and FPGA Development Environments
DESCRIPTION:<p>Liberate your FPGA / PCB environment from the monopoly of a single EDA vendor.</p>
 
END:VEVENT
BEGIN:VEVENT
DTSTAMP;VALUE=DATE:20081011T143205Z
DTSTART;VALUE=DATE-TIME:20081016T190000Z
DTEND;VALUE=DATE-TIME:20081016T200000Z
UID:http://www.fpgacentral.com/fpga-event/2008/oct/aldec%C2%AE-and-zuken%C2%AE-pin-synchronization-sm/online-thursday-october-16-2008-1100-am
URL;VALUE=URI:http://www.fpgacentral.com/fpga-event/2008/oct/aldec%C2%AE-and-zuken%C2%AE-pin-synchronization-sm/online-thursday-october-16-2008-1100-am
SUMMARY:Aldec® and Zuken®\: Pin Synchronization for Smooth Integration of PCB and FPGA Development Environments
DESCRIPTION:<p>Liberate your FPGA / PCB environment from the monopoly of a single EDA vendor.</p>
 
END:VEVENT
BEGIN:VEVENT
DTSTAMP;VALUE=DATE:20081011T143205Z
DTSTART;VALUE=DATE-TIME:20081023T140000Z
DTEND;VALUE=DATE-TIME:20081023T150000Z
UID:http://www.fpgacentral.com/fpga-event/2008/oct/euro-avms-i-04-start-using-assertions-yo/online-thursday-october-23-2008-300-pm-
URL;VALUE=URI:http://www.fpgacentral.com/fpga-event/2008/oct/euro-avms-i-04-start-using-assertions-yo/online-thursday-october-23-2008-300-pm-
SUMMARY:Euro AVMS I-04 Start Using Assertions in your Next Design
DESCRIPTION:<p>How you can start using assertion based verification without costly simulation upgrades.</p>
 
END:VEVENT
BEGIN:VEVENT
DTSTAMP;VALUE=DATE:20081011T143205Z
DTSTART;VALUE=DATE-TIME:20081023T190000Z
DTEND;VALUE=DATE-TIME:20081023T200000Z
UID:http://www.fpgacentral.com/fpga-event/2008/oct/start-using-assertions-your-next-design/online-thursday-october-23-2008-1100-am-
URL;VALUE=URI:http://www.fpgacentral.com/fpga-event/2008/oct/start-using-assertions-your-next-design/online-thursday-october-23-2008-1100-am-
SUMMARY:Start Using Assertions in your Next Design
DESCRIPTION:<p>How you can start using assertion based verification without costly simulation upgrades.</p>
 
END:VEVENT
BEGIN:VEVENT
DTSTAMP;VALUE=DATE:20081011T143205Z
DTSTART;VALUE=DATE-TIME:20081030T150000Z
DTEND;VALUE=DATE-TIME:20081030T160000Z
UID:http://www.fpgacentral.com/fpga-event/2008/oct/euro-avms-i-05-aldec-hdl-simulation-adva/online-thursday-october-30-2008-300-pm-
URL;VALUE=URI:http://www.fpgacentral.com/fpga-event/2008/oct/euro-avms-i-05-aldec-hdl-simulation-adva/online-thursday-october-30-2008-300-pm-
SUMMARY:Euro AVMS I-05 Aldec HDL Simulation Advantages over the Most Widely Marketed Simulators
DESCRIPTION:<p>Learn how to increase your simulation performance\, flexibility and lower your costs by opening your design environment to Aldec simulation solutions.</p>
 
END:VEVENT
BEGIN:VEVENT
DTSTAMP;VALUE=DATE:20081011T143205Z
DTSTART;VALUE=DATE-TIME:20081030T190000Z
DTEND;VALUE=DATE-TIME:20081030T200000Z
UID:http://www.fpgacentral.com/fpga-event/2008/oct/aldec-hdl-simulation-advantages-over-mos/online-thursday-october-30-2008-1100-am
URL;VALUE=URI:http://www.fpgacentral.com/fpga-event/2008/oct/aldec-hdl-simulation-advantages-over-mos/online-thursday-october-30-2008-1100-am
SUMMARY:Aldec HDL Simulation Advantages over the Most Widely Marketed Simulators
DESCRIPTION:<p>Learn how to increase your simulation performance\, flexibility and lower your costs by opening your design environment to Aldec simulation solutions.</p>
 
END:VEVENT
BEGIN:VEVENT
DTSTAMP;VALUE=DATE:20081011T143205Z
DTSTART;VALUE=DATE-TIME:20081104T170000Z
DTEND;VALUE=DATE-TIME:20081104T170000Z
UID:http://www.fpgacentral.com/fpga-event/11/mentor-graphics-international-unser-conf/santa-clara-ca
URL;VALUE=URI:http://www.fpgacentral.com/fpga-event/11/mentor-graphics-international-unser-conf/santa-clara-ca
SUMMARY:Mentor Graphics International Unser Conference - Santa Clara
DESCRIPTION:<p>Would you like to be more involved with planning U2U 2008?<br />
 If so\, there are two ways for you to participate\:</p>
 
END:VEVENT
BEGIN:VEVENT
DTSTAMP;VALUE=DATE:20081011T143205Z
DTSTART;VALUE=DATE-TIME:20081105T170000Z
DTEND;VALUE=DATE-TIME:20081106T003000Z
UID:http://www.fpgacentral.com/fpga-event/2008/nov/gsa-semiconductor-leaders-forum-taiwan/ambassador-hotel-hsinchu-taiwan-0
URL;VALUE=URI:http://www.fpgacentral.com/fpga-event/2008/nov/gsa-semiconductor-leaders-forum-taiwan/ambassador-hotel-hsinchu-taiwan-0
SUMMARY:GSA Semiconductor Leaders Forum - Taiwan
DESCRIPTION:<p>
 This year's Forum will feature the following presenters\, discussing<br />
 semiconductor technology and business information most relevant to your<br />
 business.
 </p>
 
END:VEVENT
BEGIN:VEVENT
DTSTAMP;VALUE=DATE:20081011T143205Z
DTSTART;VALUE=DATE-TIME:20081105T170000Z
DTEND;VALUE=DATE-TIME:20081106T000000Z
UID:http://www.fpgacentral.com/fpga-event/2008/nov/gsa-semiconductor-leaders-forum-taiwan/ambassador-hotel-hsinchu-taiwan
URL;VALUE=URI:http://www.fpgacentral.com/fpga-event/2008/nov/gsa-semiconductor-leaders-forum-taiwan/ambassador-hotel-hsinchu-taiwan
SUMMARY:GSA Semiconductor Leaders Forum - TAIWAN 
DESCRIPTION:<p>
 The GSA Semiconductor Leaders Forum TAIWAN is a must-attend event<br />
 for semiconductor industry professionals from Taiwan and around the</p>
 
END:VEVENT
BEGIN:VEVENT
DTSTAMP;VALUE=DATE:20081011T143205Z
DTSTART;VALUE=DATE-TIME:20081105T170000Z
DTEND;VALUE=DATE-TIME:20081107T020000Z
UID:http://www.fpgacentral.com/fpga-event/2008/nov/mentor-graphics-user2user-santa-clara-ca/marriott-santa-clara-ca
URL;VALUE=URI:http://www.fpgacentral.com/fpga-event/2008/nov/mentor-graphics-user2user-santa-clara-ca/marriott-santa-clara-ca
SUMMARY:Mentor Graphics User2User - Santa Clara\, CA
DESCRIPTION:<p>User2User is the annual Mentor Graphics International User Conference.<br />
 This highly interactive\, in-depth technical conference focuses on the</p>
 
END:VEVENT
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