BEGIN:VCALENDAR
VERSION:2.0
METHOD:PUBLISH
X-WR-CALNAME:FPGA Central | December 02\, 2008 - January 01\, 2009
PRODID:-//strange bird labs//Drupal iCal API//EN
BEGIN:VEVENT
DTSTAMP;VALUE=DATE:20081202T122632Z
DTSTART;VALUE=DATE-TIME:20081203T170000Z
DTEND;VALUE=DATE-TIME:20081206T023000Z
UID:http://www.fpgacentral.com/fpga-event/2008/dec/2008-international-conference-reconfigur/gran-caribe-real-cancun-mexico
URL;VALUE=URI:http://www.fpgacentral.com/fpga-event/2008/dec/2008-international-conference-reconfigur/gran-caribe-real-cancun-mexico
SUMMARY:2008 International Conference on ReConFigurable Computing and FPGAs (ReConFig'08) - Cancun\, Mexico
DESCRIPTION:ReConFig’08 will provide a leading edge forum for researchers and engineers from across the world to present their latest research and to discuss future research and applications.
END:VEVENT
BEGIN:VEVENT
DTSTAMP;VALUE=DATE:20081202T122632Z
DTSTART;VALUE=DATE-TIME:20081204T170000Z
DTEND;VALUE=DATE-TIME:20081205T020000Z
UID:http://www.fpgacentral.com/fpga-event/2008/dec/system-verilog-assertions-methodology-an/san-jose-ca
URL;VALUE=URI:http://www.fpgacentral.com/fpga-event/2008/dec/system-verilog-assertions-methodology-an/san-jose-ca
SUMMARY:SYSTEM VERILOG ASSERTIONS \:\: METHODOLOGY AND LANGUAGE TRAINING
DESCRIPTION:1 DAY SVA Training Agenda\:\:
Introduction to Assertions
What’s an assertion?
Why can’t I just use Verilog?
Advantages of Assertion Based Verification (ABV) .
END:VEVENT
BEGIN:VEVENT
DTSTAMP;VALUE=DATE:20081202T122632Z
DTSTART;VALUE=DATE-TIME:20081216T180000Z
DTEND;VALUE=DATE-TIME:20081216T220000Z
UID:http://www.fpgacentral.com/fpga-event/2008/dec/systemverilog-assertions-language-and-me/sunnyvale-ca
URL;VALUE=URI:http://www.fpgacentral.com/fpga-event/2008/dec/systemverilog-assertions-language-and-me/sunnyvale-ca
SUMMARY:SystemVerilog Assertions Language and Methodology Overview Seminar
DESCRIPTION:System Verilog Assertions (SVA) is a powerful subset of the IEEE 1800 System Verilog standard.
END:VEVENT
END:VCALENDAR